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Pin No. Pin Name
I/O
45
LRCK
O
46
DATA
O
47
BCLK
O
48
64 DATA
O
49
64 BCLK
O
50
64 LRCK
O
51
GTOP
O
52
XUGF
O
53
XPLCK
O
54
GFS
O
55
RFCK
O
56
C2PO
O
57
XRAOF
O
58
MNT3
O
59
MNT2
O
60
MNT1
O
61
MNT0
O
62
XTAI
I
63
XTAO
O
64
XTSL
I
65
DVSS
—
66
FSTI
I
67
FSTO
O
68
C4M
O
69
C16M
O
70
MD2
I
71
DOUT
O
72
EMPH
O
73
WFCK
O
L/R sampling clock signal (44.1 kHz) output to the D-RAM controller (IC680) and MPEG
audio/video decoder (IC901)
DA16 output when PSSL="H", 48-bit slot serial data output when PSSL="L"
(PSSL (pin $£)=fixed at "L") Serial data output to the D-RAM controller (IC680) and MPEG
audio/video decoder (IC901)
DA15 output when PSSL="H", 48-bit slot bit clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L") Bit clock signal (2.8224 MHz) output to the D-RAM controller
(IC680) and MPEG audio/video decoder (IC901)
DA14 output when PSSL="H", 64-bit slot serial data output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA13 output when PSSL="H", 64-bit slot bit clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA12 output when PSSL="H", 64-bit slot L/R sampling clock signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA11 output when PSSL="H", GTOP signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA10 output when PSSL="H", XUGF signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA09 output when PSSL="H", XPLCK signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA08 output when PSSL="H", GFS (guard frame sync) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA07 output when PSSL="H", RFCK (read frame clock) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA06 output when PSSL="H", C2PO signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
audio/video decoder (IC901)
DA05 output when PSSL="H", XRAOF (RAM over flow) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA04 output when PSSL="H", MNT3 (monitor 3) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA03 output when PSSL="H", MNT2 (monitor 2) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA02 output when PSSL="H", MNT1 (monitor 1) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
DA01 output when PSSL="H", MNT0 (monitor 0) signal output when PSSL="L"
(PSSL (pin $£)=fixed at "L")
Master clock signal (16.9344 MHz) input from the D/A converter (IC320)
Master clock output terminal (16.9344 MHz) Not used (open)
Master clock selection input terminal (fixed at "L")
Ground terminal (digital system)
2/3 divider input terminal of pins ^™ (XATI) and ^£ (XTAO)
2/3 divider output terminal of pins ^™ (XATI) and ^£ (XTAO)
4.2336 MHz clock signal output terminal Not used (open)
16.9344 MHz clock signal output terminal Not used (open)
Digital out on/off control signal input terminal Fixed at "H" in this set
Digital signal (for coaxial out and optical out) output terminal Not used (open)
Emphasis control signal output terminal Not used (open)
Write frame clock signal output terminal Not used (open)
– 25 –
Function
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Read frame clock signal output to the D-RAM controller (IC680)
C2PO signal output to the D-RAM controller (IC680) and MPEG
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (open)
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