Renesas QB-RL78L1C User Manual page 34

QB-RL78L1C In-Circuit Emulator
- UREGC pin voltage levels (RL78/L1C only)
UREGC pin voltage level on QB-RL78L1C differs from the target device.
Target device: 3.3V
QB-RL78L1C: Open
- TTL input buffer characteristics
If the port input mode register (PIM) is used to set the input of a pin that can be set for the TTL buffer to the TTL
level, the high-level input voltage characteristics differs from that of the target device.
Refer to a device user's manual about the pins which setting is possible to a TTL buffer.
Target device
RL78/L1C
Target device
RL78/L13
QB-RL78L1C
R20UT2703EJ0200 Rev.2.00
Jan 31, 2014
Table 4-4. Input Characteristics of TTL
Item
2.0V（3.3 V ≤ VDD ≤ 3.6 V）
VIH MIN
1.5V（1.6 V ≤ VDD < 3.3 V）
0.5V （3.3 V ≤ VDD ≤ 3.6 V）
VIL MAX
0.32V（1.6 V ≤ VDD < 3.3 V）
2.2V（4.0 V ≤ VDD ≤ 5.5 V）
2.0V（3.3 V ≤ VDD < 4.0 V）
VIH MIN
1.5V（1.6 V ≤ VDD < 3.3 V）
0.8V（4.0 V ≤ VDD ≤ 5.5 V）
0.5V（3.3 V ≤ VDD < 4.0 V）
VIL MAX
0.32V（1.6 V ≤ VDD < 3.3 V）
2.0V （3.3 V ≤ VDD ≤ 5.5 V）
VIH MIN
1.17V（1.6 V ≤ VDD < 3.3 V）
0.8V （3.3 V ≤ VDD ≤ 5.5 V）
VIL MAX
0.62V（1.6 V ≤ VDD < 3.3 V）
CHAPTER 4 CAUTIONS
Conditions
Page 34 of 42