Renesas PLQP0100KB-A User Manual page 23

Table 3 Setting a Switch (SW1)
SW1 PLQP0100KB-A
No. Socket Pin No.
1 58
2 47
3 42
4 41
5 18
6 8
7 7
8 6
Figure 3 shows a circuit for masking signals on the user system interface board.
Note: The UVcc is the Vcc in the user system.
Signal Name
PA9/_WAIT/TCLKD/_POE8/TXD2
PB1/_BREQ/TIC5W
PB6/_WAIT/CTX0
PB7/_CS1/CRX0
PE10/_CS0/TIOC3C
PE16/_WAIT/TIOC3BS
PE17/_CS0/TIOC3DS
PE18/_CS1/TIOC4AS
UVCC
PA9
PB1
PB6
PB7
User system
PE10
PE16
PE17
PE18
Figure 3 Circuit for Masking Signals
Switch Setting
On
Mask canceled
Mask canceled
Mask canceled
Mask canceled
Mask canceled
Mask canceled
Mask canceled
Mask canceled
SW1
PA9_C
PB1_C
PB6_C
PB7_C
Emulator
PE10_C
PE16_C
PE17_C
PE18_C
Off
Mask enabled
Mask enabled
Mask enabled
Mask enabled
Mask enabled
Mask enabled
Mask enabled
Mask enabled
5