Video Signal Process I Block Diagram - Panasonic NV-GS24EG Service Manual

VIDEO SIGNAL PROCESS I BLOCK DIAGRAM

MAIN P.C.B.
FROM CCD DRIVE CAMERA B1
BLOCK DIAGRAM DATA (0-9)
23-32
LUMA
TO
ANALOG VIDEO I/F
BLOCK DIAGRAM
CHROMA
LCD/EVF-R
LCD/EVF-G
TO LCD
BLOCK DIAGRAM
LCD/EVF-B
/EVF BLOCK DIAGRAM
H-SYNC
V-SYNC
ALC PWM CONTROL
TO AF
IRIS CLOSE
BLOCK DIAGRAM
IRIS OPEN
CAMERA P.C.B.
(WITH SD SLOT)
SD SLOT
B9901 B1
13,14,75,70 29,30,34,35
B9901 B1
77 77
SD B9901 B1
CARD
15 15
B9901 B1
73 73
B9901 B1
74 74
TPB(-) 1
TPB(+) 2
JK7002
DV JACK TPA(-) 3
TPA(+) 4
GND 5
JK7003 FL7001
USB LINE
JACK FILTER
R404
(WITH USB2.0 HIGH-SPEED)
IC3001 (CAMERA DIGITAL SIGNAL PROCESS/SHUFFLING)
51 52
54 61
D/A
259
CONVERTER
D/A
264
CONVERTER
D/A
242
CONVERTER
D/A
248
CONVERTER
D/A
253
CONVERTER
319 H-SYNC
318 V-SYNC
73 ALC PWM CONTROL
75 IRIS CLOSE
76 IRIS OPEN
X3002
281 48MHz CLOCK
48MHz
OSC
282 48MHz CLOCK
SD
272 275
INTERFACE
271 271 SD CLOCK
277 277 CMD
CARD DET(L)
TO SYSTEM
CONTROL
BLOCK DIAGRAM
CARD PROTECT(L)
145
148
IEEE1394
INTERFACE
150
151
(W/O USB2.0
R402
HIGH-SPEED)
291
USB
R401
INTERFACE
292
IC401 (USB INTERFACE)
R405
9 USB 68 74 201 202
INTERFACE
7 79 84 205
41 49
16 65
56 62
CAMERA SIGNAL DIGITAL SIGNAL
PROCESS PROCESS
DIS CONTROL
/ZOOM CONTROL
/EFFECT CONTROL
/JPEG
/GUI
8 11 13
MICROCONTROLLER
19 22 24 26
INTERFACE
28
215
REC VIDEO SIGNAL PB VIDEO SIGNAL
161
DV FORMAT
INTERFACE
164
168
169
171
173
27MHz CLOCK 102
READ(H) 175
DRAM
VAL 174
HEAD SW PULSE 1 159
183
178
AUDIO
DIGITAL
180
SIGNAL
PROCESS
182
181
CAMERA DAC/TG SERIAL CLOCK 302
DRAM
CAMERA DAC/TG SERIAL DATA 300
TG CS(L) 303
FCK (18MHz) 48
CAM VD 50
CAM HD 49
CAMERA DAC CS(L) 304
IC6001 (SYSTEM MICROCONTROLLER)
L13 L14 M13 M14
16 ADM (0 -15)
N15 N17 N18 MICROCONTROLLER
INTERFACE
P15 P18 R16 R18
T17 T18
VIDEO SIGNAL PROCESS I BLOCK DIAGRAM
NV-GS24EG, NV-GS26GK, NV-GS27E/EB/EF/EG/EP/EE/GC/GN,
NV-GS37E/EB/EG/EK/EP, NV-GS47EE/GC, NV-GS57EE/GC, NV-GS58GK
REC AUDIO SIGNAL PB AUDIO SIGNAL
DBR DATA (4 BIT)
DBR(0 -3)
ADDA (4BIT)
ADDA(0 -3)
TO/FROM
VIDEO SIGNAL
PROCESS II
BLOCK
DIAGRAM
27MHz CLOCK
READ(H)
VAL
HEAD SW PULSE 1
AUDIO DATA 0
AUDIO DATA 1 TO/FROM
AUDIO SIGNAL
AUDIO L/R CLOCK PROCESS
BLOCK
DIAGRAM
AUDIO BIT CLOCK
AUDIO MASTER CLOCK
B1
CG/AFE SERIAL CLOCK
64
B1
CG/AFE SERIAL DATA
65
B1
CG CS(L)
67
B1 TO/FROM
FCK (18MHz)
CCD DRIVE
59
BLOCK
B1
DIAGRAM
CAM VD
68
B1
CAM HD
69
B1
CAMERA AFE CS(L)
66
B1
12MHz CLOCK
60