DAEWOO ELECTRONICS DSL-19M1WCD Service Manual page 18

Pin Name No
GPIO14/PWM3/ 52
SCART16
TDO 55
HSYNC1 156
VSYNC1 157
101
102
XOSD_CLK 103
XOSD_HS 104
PD20/B4/GPIO0 86
PD21/B5/GPIO1 87
PD22/B6/GPIO2 88
PD23/B7/GPIO3 89
Table 6: LVDS Display Interface
Pin Name No
PBIAS 53
PPWR 54
AVDD_LV_33 56
VCO_LV 57
AVSS_LV 58
AVDD_OUT_LV_33 59
60
CH3P_LV_E
CH3N_LV_E 61
CLKP_LV_E 62
CLKN_LV_E 63
64
CH2P_LV_E
65
CH2N_LV_E
CH1P_LV_E 66
CH1N_LV_E 67
CH0P_LV_E 68
69
CH0N_LV_E
AVSS_OUT_LV 70
AVDD_OUT_LV_33 71
CH3P_LV_O 72
CH3N_LV_O 73
74
CLKP_LV_O
CLKN_LV_O 75
CH2P_LV_O 76
CH2N_LV_O 77
CH1P_LV_O 78
79
CH1N_LV_O
CH0P_LV_O 80
CH0N_LV_O 81
AVSS_OUT_LV 82
AVDD_OUT_LV_33 83
I/O Description
IO This Pin can be programmed to give out Pulse Width Modulated Output Pulses for external use.
Or it can be programmed to sense the Fast Blank Input signal from a SCART I/P source. When
not used, this pin is available as General Purpose Input/output Port.
O This Pin provides the Output Data in case of Boundary Scan Mode.
I Horizontal Sync signal Input-1. Used when Analog RGB component signal carries separate
HSYNC signal.
I Vertical Sync signal Input-1. Used when Analog RGB component signal carries separate VSYNC
signal.
O Clock Output meant for External OSD Controller
O Horizontal Sync Output meant for External OSD Controller
O Vertical Sync Output meant for External OSD Controller
O Field Signal Output meant for External OSD Controller
IO These Pins provide the Panel Data as shown in the TTL Display Interface Table below. These are
available as General Purpose Input / Output Pins when not used as Panel Data.
I/O Description
O Panel Bias Control (backlight enable) [Tri-state output, 5V- tolerant]
O Panel Power Control [Tri-state output, 5V- tolerant]
DP Digital Power for LVDS Block. Connect to digital 3.3V supply.
O Reserved. Output for Testing Purpose only at Factory.
G Ground for LVDS outputs.
DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
O These form the Differential Data Output for Channel – 3 (Even).
O
O These form the Differential Clock Output Even Channel.
O
O These form the Differential Data Output for Channel – 2 (Even).
O
O These form the Differential Data Output for Channel – 1 (Even).
O
O These form the Differential Data Output for Channel – 0 (Even).
O
G Ground for LVDS outputs.
DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.
O These form the Differential Data Output for Channel – 3 (Odd).
O
O These form the Differential Clock Output Odd Channel.
O
O These form the Differential Data Output for Channel – 2 (Odd).
O
O These form the Differential Data Output for Channel – 1 (Odd).
O
O These form the Differential Data Output for Channel – 0 (Odd).
O
G Ground for LVDS outputs.
DP Digital Power for LVDS outputs. Connect to digital 3.3V supply.