DAEWOO ELECTRONICS DSL-19M1WCD Service Manual page 16

SVN 204 AI
VO_GND 205 AG
VOUT2 206 AO
VDD18_SC 207 AP
GND18_SC 208 AG
Table 2: Low Bandwidth ADC Input Port
Pin Name No I/O
VDDA33_LBADC 1 AP
LBADC_IN1 2 AI
LBADC_IN2 3 AI
LBADC_IN3 4 AI
LBADC_IN4 5 AI
LBADC_IN5 6 AI
LBADC_IN6 7 AI
LBADC_RTN 8 AG
VSSA33_LBADC 9 AG
Table 3: RCLK PLL Pins
Pin Name No I/O
GND_RPLL 11 DG
VDD_RPLL_18 12 DP
VBUFC_RPLL 13 O
AGND_RPLL 14 AG
XTAL 15 AO
TCLK 16 AI
AVDD_RPLL_33 17 AP
Table 4: Digital Video Input Port
Pin Name No I/O
VID_CLK_1 153 I
VIDIN_HS 122 I
VIDIN_VS 121 I
VID_DATA_IN_0 135 IO
VID_DATA_IN_1 136
VID_DATA_IN_2 137
VID_DATA_IN_3 138
VID_DATA_IN_4 139
VID_DATA_IN_5 140
VID_DATA_IN_6 141
VID_DATA_IN_7 142
Negative analog sync input for channels 1 through 4.
This acts as the return Path for the Sources connected to SV Channel Inputs. This has to be AC coupled
using a series 20 Ohm resistor and 0.1uF Capacitor network to Analog Ground Plane on board.
Analog Ground. Must be directly connected to the analog system ground plane on board.
Analog VOUT signal
This is the Analog Video Output from the Decoder in the Composite Video format. This can be amplified
and be fed to any video display device.
Analog Power (1.8V) for SYNC Channel. Must be bypassed with 0.1uF capacitor to the analog system
ground plane.
Analog Ground (1.8V Return) for SYNC channel. Must be directly connected to the analog system ground
plane on board.
Description
Analog Power (3.3V) for Low Bandwidth ADC Block. Must be bypassed with 0.1uF capacitor.
Low Bandwidth Analog Input-1. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
Low Bandwidth Analog Input-2. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
Low Bandwidth Analog Input-3. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
Low Bandwidth Analog Input-4. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
Low Bandwidth Analog Input-5. The Input signal connected to this Pin, must be bypassed with a 0.1uF
capacitor and could be in the range of 0V to 3.3V (peak to peak).
Low Bandwidth Analog Input-6. The Input signal connected to this Pin, must be bypassed with
This Pin provides the Return Path for LBADC inputs. Must be directly connected to the analog system
ground plane on board.
Analog Ground for Low Bandwidth ADC Block. Must be directly connected to the analog system ground
plane on board.
Description
Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground plane.
Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to Ground Plane.
Test Output. Leave this Pin Open. This is reserved for Factory Testing Purpose.
Analog ground for the Reference DDS PLL. Must be directly connected to the analog system ground
plane.
Crystal oscillator output.
Reference clock (TCLK) from the 14.3MHz crystal oscillator.
Analog Power (3.3V) for RCLK PLL. Must be bypassed with 0.1uF capacitor.
Description
Video port data clock input meant for Video Input – 1. Up to 75Mhz
[Input, 5V-tolerant]
When Video Input – 1 is in BT656 Mode, this Pin acts as Horizontal Sync Input for Video Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Horizontal Sync Input for Video Input – 1.
OR this Pin acts as Horizontal Sync Input for 24 Bit Video Input
When Video Input – 1 is in BT656 Mode, this Pin acts as Vertical Sync Input for Video Input – 2.
OR when Video Input – 1 is in 16 Bit Mode this Pin acts as Vertical Sync Input for Video Input – 1.
OR this Pin acts as Vertical Sync Input for 24 Bit Video Input
Input YUV data in 8-bit BT656 of Video Input – 1
[Bi-Directional, 5V-tolerant]
OR Input Y Data in case of 16 Bit Video Input (CCIR601) of Video Input – 1
OR Input Red Data in case of 24 Bit Video Input