Ethernet Interface - Fluke 2640A Service Manual

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Service Manual
Data Terminal Ready (DTR) and Request To Send (RTS) are modem control signals
controlled by the Microprocessor. When the instrument is powered up, the
Microprocessor initially sets DTR and RTS false by setting A1U1-61 and A1U1-59 high,
which results in the RS-232 driver outputs (A1U13-7 and A1U13-5 respectively) going
to -5.0V dc. When the instrument has initialized the RS-232 interface and is ready to
receive and transmit, A1U1-61 and A1U1-59 goes low, resulting in the RS-232 DTR and
RTS signals going to +5.0V dc. The RS-232 DTR and RTS signals remain at +5.0V dc
until the instrument is powered down except for a short period of time when the user
changes RS-232 communication parameters from the front panel of the instrument.
Clear To Send (CTS) and Data Set Ready (DSR) are modem control inputs from the
connected RS-232 equipment. Of these signals, only CTS is used when CTS flow control
is enabled via the RS-232 communication setup menu. The CTS modem control signal
from A1J4 goes to the RS-232 receiver A1U13-6, which inverts and level shifts the
signal so that the input to the Microprocessor (A1U1-58) transitions between 0 and
+5.0V dc. When the instrument is cleared to send characters to the RS-232 interface, the
receiver output (A1U13-11) is +5.0V dc. If the RS-232 CTS signal is not driven by the
attached RS-232 equipment, the receiver output (A1U13-11) is near 0V dc.

Ethernet Interface

The Ethernet Interface is the primary means the instrument uses to communicate with a
host computer. The interface is comprised of an Ethernet chip, a buffer memory, two
physical connectors, and electrically isolated interfaces between the Ethernet chip and
the connectors. Only one of the two connectors are used at a time.
Ethernet Chip and Buffer Memory The Ethernet chip (A1U32) is directly connected
to the Microprocessor's address and data bus. Three address lines are used to select
registers within the Ethernet Chip, and data is transferred over 16 data lines. The chip
select is performed by read and write strobe signals EIOR* and EIOW* (A1U32-154 and
A1U32-155). EIOR* is driven low when the Microprocessor is reading from the
Ethernet Chip, and EIOW* is driven low when the Microprocessor is writing to the
Ethernet Chip. The Ethernet chip signals the end of a read or write cycle by driving its
RDY output (A1U32-151) low. This enables the output of tri-state buffer A1U2-3,
driving the DTACK* signal low to the Microprocessor (A1U1-85). When the
Microprocessor sees DTACK* go low, it ends the read or write cycle to the Ethernet
chip. The Ethernet Chip may also interrupt the Microprocessor by driving EINT* low
(A1U32-133.) A1R133 is used to pull EINT* high.
Unlike RS-232 and other serial interfaces, Ethernet transfers data as packets of several K
bytes of data, instead of as single bytes. The buffer memory is used to store packets
while they are being received, or while being transmitted. The Ethernet Chip (A1U32) is
connected directly to the buffer memory (A1U33). Packets being received or transmitted
are stored to or retrieved from the buffer memory by the Ethernet Chip. The buffer
memory (A1U33) provides 32K bytes of storage for data packets.
Packets stored in the buffer memory (A1U33) are transferred to or from the Static RAM
(A1U20, A1U30, A1U34, or A1U35) by a DMA controller in the Microprocessor
(A1U1). This transfer is done with read or write cycles to the Ethernet Chip (A1U32).
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