ST AN3959 Application Note
  1. Manuals
  2. Brands
  3. ST Manuals
  4. Motherboard
  5. AN3959
  6. Application note
ST AN3959 Application Note

ST AN3959 Application Note

2.0-channel demonstration board based on the sta381bw and sta381bws
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Introduction
The purpose of this application note is to describe:
■
how to connect the STA381BW/STA381BWS 2.0-channel demonstration board
■
how to evaluate the performance of the demonstration board with significant electrical
curves
■
how to avoid critical issues in the PCB schematic and layout of the
STA381BW/STA381BWS
The STA381BW/STA381BWS demonstration board is configured for 2.0 BTL channels,
releasing up to 2 x 20 W into 8 ohm of power output at 18 V of supply voltage in the VQFN48
package. It represents a total solution for the digital audio power amplifier.
Figure 1.
STA381BW/STA381BWS 2.0-channel demonstration board
December 2011
2.0-channel demonstration board
based on the STA381BW and STA381BWS
Doc ID 022081 Rev 3
AN3959
Application note
1/65
www.st.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AN3959 and is the answer not in the manual?

Questions and answers

Related Manuals for ST AN3959

Summary of Contents for ST AN3959

  • Page 1: Figure 1. Sta381Bw/Sta381Bws 2.0-Channel Demonstration Board

    AN3959 Application note 2.0-channel demonstration board based on the STA381BW and STA381BWS Introduction The purpose of this application note is to describe: ■ how to connect the STA381BW/STA381BWS 2.0-channel demonstration board ■ how to evaluate the performance of the demonstration board with significant electrical curves ■...

  • Page 2: Table Of Contents

    Layout ........... . 31 Software setup to use the STA381BW/STA381BWS devices (ST Map) .
  • Page 3 AN3959 Contents CRC computation ......... . . 45 7.3.1...
  • Page 4 List of figures AN3959 List of figures Figure 1. STA381BW/STA381BWS 2.0-channel demonstration board ......1 Figure 2.
  • Page 5 AN3959 List of figures Figure 49. STCompressor - limiter threshold ..........40 Figure 50.

  • Page 6: Functional Description Of The Demonstration Board

    Functional description of the demonstration board AN3959 Functional description of the demonstration board The following terms used in this application note are defined as follows: ● THD+N vs. Freq: Total harmonic distortion (THD) plus noise versus frequency curve ● THD+N vs. Pout: Total harmonic distortion (THD) plus noise versus output power ●...

  • Page 7: Schematic And Block Diagrams, Bill Of Material, Pcb Layout

    Schematic and block diagrams, bill of material, PCB layout Figure 2. Schematic-1 SWPA6045S220MT OUT1A +3V3 RESET 220nF 0 ohm 0 ohm 220nF SWPA6045S220MT OUT1B 100nF OUT2A SWPA6045S220MT 220nF OUT2B LRCKI BICKI 220nF MCLK VCC_REG MCLK SPEAKJACK2X2 VSS_REG AGNDPLL OUT2B C3 2u2/10V OUT2B VREGFILT SWPA6045S220MT...

  • Page 8: Figure 3. Schematic-2

    Figure 3. Schematic-2 100uF 220PF FFX3B BEAD or 33R 47uF 100nF 470PF 150PF LM833 HEADPHONE O/P 100PF 100PF OUTA 100uF INA1 OUTB INA2 FFX3A INB1 BEAD or 33R INB2 FFX4B 220PF 220PF 470PF 150PF FFX4A STEREO HEADPHONE DRIVER FFX3A J3-1 MCLK J8-1 +3V3...
  • Page 9 AN3959 Functional description of the demonstration board Table 1. Bill of material Type Footprint Description Reference Manufacturer Jack Speaker jack MP4-16 Songchen Headphone SONGCHEN CKX-3.5-06 Phone jack J2, J13, J19 Songchen jack 3-pin Deviator Switch Deviator switch SW2, SW3 Any source...
  • Page 10 Functional description of the demonstration board AN3959 Table 1. Bill of material (continued) Type Footprint Description Reference Manufacturer R1206 R10, R11, R30, R41 Murata R1206 20 +/-5% 1/8W R42, R43 Murata R0603 0 ohm 1/16W R1, R3, R36 Murata R0603...

  • Page 11: Figure 4. Top View Of Pcb Layout

    AN3959 Functional description of the demonstration board Figure 4. Top view of PCB layout Doc ID 022081 Rev 3 11/65...

  • Page 12: Figure 5. Inner Layer2 View Of Pcb Layout

    Functional description of the demonstration board AN3959 Figure 5. Inner layer2 view of PCB layout 12/65 Doc ID 022081 Rev 3...

  • Page 13: Figure 6. Inner Layer3 View Of Pcb Layout

    AN3959 Functional description of the demonstration board Figure 6. Inner layer3 view of PCB layout Doc ID 022081 Rev 3 13/65...

  • Page 14: Figure 7. Bottom View Of Pcb Layout

    Functional description of the demonstration board AN3959 Figure 7. Bottom view of PCB layout 14/65 Doc ID 022081 Rev 3...

  • Page 15: Figure 8. Block Diagram Of Test Connections With Equipment

    AN3959 Functional description of the demonstration board Figure 8. Block diagram of test connections with equipment Audio Precision Equipment Monitor Output S/PDIF to AP Signal Digital Oscilloscope TDS3034B Tektronix APWLink Board S Input STA380BWS (DC3V3) 2.0CH Demo Board (DC7V) PC with GUI to control the...

  • Page 16: Sta381Bws Power Section Test Results

    STA381BWS power section test results AN3959 STA381BWS power section test results Figure 9. Frequency response, V = 18 V, R = 8 ohm, 0 dB (Pout = 1 W) +2.5 +1.5 +0.5 -0.5 -1.5 -2.5 Test Conditions : VCC=18V, Rl=8ohm, Dual BTL, Input Signal=-14dBFS, Pout=1W, Volume: +3dB Figure 10.

  • Page 17: Figure 11. Snr, Vcc = 18 V, R L = 8 Ohm, 0 Db (Pout = 1 W)

    AN3959 STA381BWS power section test results Figure 11. SNR, V = 18 V, R = 8 ohm, 0 dB (Pout = 1 W) -100 Test Conditions : VCC=18V, Rl=8ohm, Dual BTL, Pout=1W, Volume: +3dB Figure 12. THD vs. frequency, V...

  • Page 18: Figure 13. Fft (0 Dbfs), Vcc = 18 V, R L = 8 Ohm, 0 Dbfs (Pout = 1 W)

    STA381BWS power section test results AN3959 Figure 13. FFT (0 dBFS), V = 18 V, R = 8 ohm, 0 dBFS (Pout = 1 W) -100 -110 -120 -130 -140 Test Conditions : VCC=18V, Rl=8ohm, f=1KHz, Dual BTL, Input Signal=0dBFS, Pout=1W, Volume: -11.5dB Figure 14.

  • Page 19: Figure 16. Thd Vs. Output Power At Different Power Supplies, R

    AN3959 STA381BWS power section test results Figure 15. THD vs. output power, V = 18 V, R = 8 ohm, f = 1 kHz 0.05 0.02 0.01 100m 200m 500m Test Conditions : VCC=18V, Rl=8ohm, Dual BTL, Volume: +3dB Figure 16. THD vs. output power at different power supplies, R...

  • Page 20: Sta381Bw Power Section Test Results

    STA381BW power section test results AN3959 STA381BW power section test results Figure 17. Frequency response, V = 24 V, R = 8 ohm, 0 dB (Pout = 1 W) +2.5 +1.5 +0.5 -0.5 -1.5 -2.5 Test Conditions : VCC=24V, Rl=8ohm, Dual BTL, Input Signal=-17dBFS, Pout=1W, Volume: +3dB Figure 18.

  • Page 21: Figure 19. Snr, Vcc = 24 V, R L = 8 Ohm, 0 Db (Pout = 1 W)

    AN3959 STA381BW power section test results Figure 19. SNR, V = 24 V, R = 8 ohm, 0 dB (Pout = 1 W) -100 Test Conditions : VCC=24V, Rl=8ohm, Dual BTL, Pout=1W, Volume: +3dB Figure 20. THD vs. frequency, V...

  • Page 22: Figure 21. Fft (0 Dbfs), Vcc = 24 V, R L = 8 Ohm, 0 Dbfs (Pout = 1 W)

    STA381BW power section test results AN3959 Figure 21. FFT (0 dBFS), V = 24 V, R = 8 ohm, 0 dBFS (Pout = 1 W) -100 -110 -120 -130 -140 Test Conditions : VCC=24V, Rl=8ohm, f=1KHz, Dual BTL, Input Signal=0dBFS, Pout=1W, Volume: -13.5dB Figure 22.

  • Page 23: Figure 15. Thd Vs. Output Power

    AN3959 STA381BW power section test results Figure 23. THD vs. output power, V = 24 V, R = 8 ohm, f = 1 kHz 0.05 0.02 0.01 100m 200m 500m Test Conditions : VCC=24V, Rl=8ohm, Dual BTL, Volume: +3dB Figure 24. THD vs. output power at different power supplies, R...

  • Page 24: Analog Section Test Results

    Analog section test results AN3959 Analog section test results The line/headphone out can be fed either with an external analog source, or with the F3X output, allowing the audio content to come from the digital interface on both the power output and on the line/headphone out.
  • Page 25 AN3959 Analog section test results Table 4. Line out section test results Filter: 22K LPF Ext Res: 18K + 43K Line out Unit Spec. Test results Reference 200 mV +/-20% Maximum output level Left mVrms 2.0 V↓ 1.86 1.87 Right Frequency response -1 dB↑,+0.5dB↓...

  • Page 26: Thermal Performance

    Thermal performance AN3959 Thermal performance Thermal results - test 1 Figure 25. Temperature test 1 Testing conditions: ● = 12 V ● 1 kHz sine wave ● 8 ohm Output power: 2 x 7 W Table 5. Thermal results - test 1 Result Tamb = 25 °C...

  • Page 27: Thermal Results - Test 2

    AN3959 Thermal performance Thermal results - test 2 Figure 26. Temperature test 2 Testing conditions: ● = 24 V ● 1 kHz sine wave ● 8 ohm Output power: 2 x 15 W Table 6. Thermal results - test 2 Result Tamb = 25 °C...

  • Page 28: Design Guidelines For Schematic And Pcb Layout

    Design guidelines for schematic and PCB layout AN3959 Design guidelines for schematic and PCB layout Schematic 6.1.1 Criteria for selection of components ● Absolute maximum rating: STA381BWS V = 27 V ● Bypass capacitor 100 nF in parallel to 1 µF for each power V branch.

  • Page 29: Snubber Filter

    AN3959 Design guidelines for schematic and PCB layout 6.1.4 Snubber filter The snubber circuit must be optimized for the specific application. Starting values are 330 pF in series to 22 ohm. The power on this network is dependent on the power supply,...

  • Page 30: Main Filter

    Design guidelines for schematic and PCB layout AN3959 6.1.5 Main filter The main filter is an L and C based Butterworth filter. The cutoff frequency must be chosen between the upper limit of the audio band (≈20 kHz) and the carrier frequency (384 kHz).

  • Page 31: Recommended Power-Up And Power-Down Sequence

    AN3959 Design guidelines for schematic and PCB layout 6.1.7 Recommended power-up and power-down sequence There is no constraint regarding power supply voltages while it is required to release the reset line (RST) only after the master clock (MCLK) is stable, after the power-down (PWDN) is already set high and before any I C commands.

  • Page 32: Figure 34. Electrolytic Capacitor Used First To Separate The Vcc Branches

    Design guidelines for schematic and PCB layout AN3959 Figure 34. Electrolytic capacitor used first to separate the V branches Figure 35. Path between V and ground pin minimized in order to avoid inductive paths 32/65 Doc ID 022081 Rev 3...

  • Page 33: Figure 36. Large Ground Plane On The Top Side

    AN3959 Design guidelines for schematic and PCB layout Thermal dissipation It is mandatory to have a large ground plane on the top layer, inner layer2, inner layer3, and bottom layer and solder the slug on the PCB. Figure 36. Large ground plane on the top side Figure 37.

  • Page 34: Figure 38. Large Ground Plane On Inner Layer3

    Design guidelines for schematic and PCB layout AN3959 Figure 38. Large ground plane on inner layer3 34/65 Doc ID 022081 Rev 3...

  • Page 35: Figure 39. Large Ground Plane On Bottom Side

    AN3959 Design guidelines for schematic and PCB layout Figure 39. Large ground plane on bottom side Figure 40. Symmetrical paths created for output stage, for differential applications Doc ID 022081 Rev 3 35/65...

  • Page 36: Figure 41. Coils Separated In Order To Avoid Crosstalk

    Design guidelines for schematic and PCB layout AN3959 Figure 41. Coils separated in order to avoid crosstalk Figure 42. V filter for high frequency Placing the V filter capacitors close to the pins avoids an inductive coil generated by the copper wire, because the system is working in PWM with fast switching (the frequency is 384 kHz with fs = 48 kHz) so the longer copper wire easily becomes an inductor.

  • Page 37: Figure 43. Thermal Layout With Large Ground

    AN3959 Design guidelines for schematic and PCB layout Figure 43. Thermal layout with large ground The thermal resistance junction in the bottom of the STA381BWS to ambient, obtainable with a ground copper area of 5.6 x 5.6 mm and with 16 via holes is shown in...

  • Page 38: Software Setup To Use The Sta381Bw/Sta381Bws Devices (St Map)

    Software setup to use the STA381BW/STA381BWS devices (ST Map) AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) Processing configuration Figure 44. Processing path Pro c es s ing F requency = 2x F s X2O v er- Biq uad #5...

  • Page 39: Stcompressor

    AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) STCompressor Figure 46. STCompressor - overview DRC0 Offset Level Mapper Attenuator Output Meter Input Level Attenuator Mapper Meter Offset Band Splitter DRC1 DRC2 Offset Level Mapper Attenuator Output Input Meter...

  • Page 40: Figure 48. Stcompressor - Compression Ratio

    Software setup to use the STA381BW/STA381BWS devices (ST Map) AN3959 Figure 48. STCompressor - compression ratio ● The compression ratio is user-programmable ● By default the rate is 1:1 (no variable ratio) ● There are 16 different settings (from 0 to 15) and the ratio varies from 1:1 to 1:16 Figure 49.

  • Page 41: Stcompressor Settings

    AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) Figure 50. STCompressor - offset control ● The offset is a user-programmable gain or volume control ● When the STC is used, it is better to use offset instead of volume for location in the processing path There are 192 different settings (from 0 to +48) with 0.25 dB/step...

  • Page 42: Example Settings Of The Stcompressor

    Software setup to use the STA381BW/STA381BWS devices (ST Map) AN3959 7.2.3 Example settings of the STCompressor Band splitter: ● Biquad 0, biquad 1 of band 0: low-pass filter with Fc = 200 Hz Write in RAM the following values. BQ0 band 0: 0x40→0x000059...
  • Page 43 AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) Compression ratio - 1:2 = 4 ● Coefficient value = HEX [(4/2 ) * 2 ] = HEX (524288) = 0x080000 ● Write in RAM: – 0x57→0x080000 – 0x61→0x080000 Attack rate: +4 dB/msec ●...

  • Page 44: Test Results With Apworkbench

    Software setup to use the STA381BW/STA381BWS devices (ST Map) AN3959 7.2.4 Test results with APWorkbench The following figure shows the APWorkbench results for the example settings given in Section 7.2.3. Figure 51. APWorkbench results for STC example 44/65 Doc ID 022081 Rev 3...

  • Page 45: Crc Computation

    AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) CRC computation In the STA381BW/STA381BWS there are three different CRCs: ● Biquad ● Crossover ● STCompressor 7.3.1 Biquad CRC computation ● Download into RAM the biquad filter coefficients (address 0x00-0x27) ●...

  • Page 46: Stcompressor Tm Crc Computation

    Software setup to use the STA381BW/STA381BWS devices (ST Map) AN3959 7.3.3 STCompressor CRC computation ● Download into RAM the STC band splitter filter coefficients into the RAM (address 0x40-0x53) ● The XOR function calculates bit-to-bit the downloaded coefficients ● Write into RAM the expected value (address 0x72 – CRC expected) ●...

  • Page 47: Startup

    AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) Startup ST map selection ● Select register map (ST Map) – 0x7E (MISC4) bit D7 (SMAP) set to 0 (default is 1) Clock and SAI configuration ● Set clock selection (register 0x00) –...

  • Page 48: Figure 52. F3X Output

    Software setup to use the STA381BW/STA381BWS devices (ST Map) AN3959 Figure 52. F3X output Note: If the digital input is 0 dBFs, the F3X output is 1.8 Vpp (that means 0.64 Vrms). F3X for HPout ● Write in register 0x58 (F3XCFG1) the value 0x80 (default value 0x00) which enables the F3XLNK function.

  • Page 49: Short-Circuit Protection For The Sta381Bw/Sta381Bws

    AN3959 Software setup to use the STA381BW/STA381BWS devices (ST Map) Short-circuit protection for the STA381BW/STA381BWS The device is protected to short circuit at power-on: ● Enable the short-circuit check enable bit (SHEN, bit D0 register 0x4C) ● When the device switches from EAPD = 0 to EAPD = 1 (bit D7 register 0x05), the protection checks the short-circuit ●...

  • Page 50: Examples Of Code (Tv Soc)

    Examples of code (TV SoC) AN3959 Examples of code (TV SoC) FFX381X_Sample.h #ifndef FFX_38X_H #define FFX_38X_H //#define FFX_I2C_ADDR 0x34 #define FFX_I2C_ADDR 0x38 #define FFX_CONFIGURE_A 0x00 #define FFX_CONFIGURE_B 0x01 #define FFX_CONFIGURE_C 0x02 #define FFX_CONFIGURE_D 0x03 #define FFX_CONFIGURE_E 0x04 #define FFX_CONFIGURE_F 0x05...
  • Page 51 AN3959 Examples of code (TV SoC) #define FFX_L2AR_RATE 0x14 #define FFX_L2AR_THRESHOLD 0x15 #define STA381BWX_NEWMAP 0x80 #define STA381BWX_STMAP 0x00 #define STA381BWX_MAPSEL 0x7E #define STA381BWX_Cross_userdefine 0x00 #define STA381BWX_Cross_80Hz 0x01 #define STA381BWX_Cross_100Hz 0x02 #define STA381BWX_Cross_120Hz 0x03 #define STA381BWX_Cross_140Hz 0x04 #define STA381BWX_Cross_160Hz 0x05 #define STA381BWX_Cross_180Hz...
  • Page 52 Examples of code (TV SoC) AN3959 void STA381BWX_SetRightVolume(unsigned char RightVolume); void STA381BWX_SetSubWooferVolume(unsigned char SubWooferVolume); void STA381BWX_CrossOver(unsigned char FFX_CrossOverValue); void STA381BWX_Poweronoff(unsigned char FFX_Powerflag); void STA381BWX_Powerdownonoff(unsigned char FFX_Powerflag); void STA381BWX_DSPBypass(unsigned char DSPBypassFlag); void STA381BWX_DeEmphasis(unsigned char DeEmphasisFlag); void STA381BWX_FilterLink(unsigned char FilterlinkFlag); void STA381BWX_PostscaleLink(unsigned char PostscalelinkFlag);...

  • Page 53: Ffx381X_Sample.c

    AN3959 Examples of code (TV SoC) FFX381X_Sample.C #include "FFX38X_Sample.h" /* This is the reference source code of STA381BWX series FFX amplifier function reference: I2Cm_Tx(&valueReg,RegAddress,1,DeviceAddress);//write the data to I2C register,DeviceAddress=FFX_I2C_ADDR I2Cm_Rx(&valueReg,RegAddress,1,DeviceAddress);//Read the data from I2C register,DeviceAddress=FFX_I2C_ADDR unsigned char oldMasterVolume; unsigned char oldLeftVolume;...
  • Page 54 Examples of code (TV SoC) AN3959 I2C_buf1=FilterIndex*5; I2Cm_Tx(&I2C_buf1,0x16,1,FFX_I2C_ADDR); //Write the command to 0x26(3 times) I2C_buf1=0x08; I2Cm_Tx(&I2C_buf1,0x26,1,FFX_I2C_ADDR); I2Cm_Tx(&I2C_buf1,0x26,1,FFX_I2C_ADDR); I2Cm_Tx(&I2C_buf1,0x26,1,FFX_I2C_ADDR); Wait(10);//10-20ms delay //read bank data from 0x17~0x25 for(STA381BWX_tempj=0;STA381BWX_tempj<15;STA381BWX_tempj++){ I2Cm_Rx(&I2C_buf1,(0x17+STA381BWX_tempj),1,FFX_I2C_ADDR); STA381BWX_EQ[STA381BWX_tempj]=I2C_buf1; Intial the EQ curve for coefficient data Write write Filter data from STA381_EQ[],Filter address FilterIndex=0~4 void STA381BWX_CoefficientWrite(unsigned char FilterIndex) unsigned char STA381BWX_tempj;...
  • Page 55 AN3959 Examples of code (TV SoC) //Write the command to 0x26(3 times) I2C_buf1=0x02; I2Cm_Tx(&I2C_buf1,0x26,1,FFX_I2C_ADDR); initial the system output configuration as below FFX_Configuration=0; 2.0 2*BTL setting with HP FFX_Configuration=1; 2.1 2*SE+1*BTL setting FFX_Configuration=2; 2.1 2*BTL+1*PWMoutput(driver Power stage) setting FFX_Configuration=3; .1 mono BTL setting...
  • Page 56 Examples of code (TV SoC) AN3959 void STA381BWX_Powerdownonoff(unsigned char FFX_Powerflag){ I2Cm_Rx(&I2C_buf1,FFX_CONFIGURE_F,1,FFX_I2C_ADDR); I2C_buf1&=0xBF; I2C_buf1+=((FFX_Powerflag)<<6); I2Cm_Tx(&I2C_buf1,FFX_CONFIGURE_F,1,FFX_I2C_ADDR); Set Crossover FFX_CrossOver value have define as constant value void STA381BWX_CrossOver(unsigned char FFX_CrossOverValue){ I2Cm_Rx(&I2C_buf1,FFX_AUTO2,1,FFX_I2C_ADDR); I2C_buf1&=0x0F; I2C_buf1+=(FFX_CrossOverValue<<4); I2Cm_Tx(&I2C_buf1,FFX_AUTO2,1,FFX_I2C_ADDR); /* the volume system consist of main volume and channel volume, the main volume is responsible for the overall system control, it's range from -127.5dB to 0dB, every step as 0.5dB,...
  • Page 57 AN3959 Examples of code (TV SoC) I2Cm_Rx(&I2C_buf1,FFX_MAIN_VOLUME,1,FFX_I2C_ADDR); MUTEVolSave = I2C_buf1; // Save the current Gain I2C_buf1=0xFE; I2Cm_Tx(&I2C_buf1,FFX_MAIN_VOLUME,1,FFX_I2C_ADDR); Wait(10);//10-20ms delay else I2Cm_Tx(&MUTEVolSave,FFX_MAIN_VOLUME,1,FFX_I2C_ADDR); Wait(10);//10-20ms delay return; /*the channel volume is responsible for the each channel volume control, it's range from -79.5dB to 48dB, every step as 0.5dB, channelvolume=255-((dbrequest+79.5)*2);...
  • Page 58 Examples of code (TV SoC) AN3959 return; Set the FFX DSP bypass or not DSPBypassFlag=0;DSP not bypass DSPBypassFlag=1;DSP bypass void STA381BWX_DSPBypass(unsigned char DSPBypassFlag) I2Cm_Rx(&I2C_buf1,FFX_CONFIGURE_D,1,FFX_I2C_ADDR); I2C_buf1&=0xFB; I2C_buf1+=(DSPBypassFlag<<2); I2Cm_Tx(&I2C_buf1,FFX_CONFIGURE_D,1,FFX_I2C_ADDR); Set the FFX DeEmphasis or not DeEmphasisFlag=0; DeEmphasis disable DeEmphasisFlag=1; DeEmphasis enable void STA381BWX_DeEmphasis(unsigned char DeEmphasisFlag) I2Cm_Rx(&I2C_buf1,FFX_CONFIGURE_D,1,FFX_I2C_ADDR);...
  • Page 59 AN3959 Examples of code (TV SoC) I2C_buf1+=(FilterlinkFlag<<4); I2Cm_Tx(&I2C_buf1,FFX_CONFIGURE_D,1,FFX_I2C_ADDR); Set the FFX PostScale Link or not PostscalelinkFlag=0;each channel use the own filter PostscalelinkFlag=1;each channel's filter setting same as channel1's void STA381BWX_PostscaleLink(unsigned char PostscalelinkFlag) I2Cm_Rx(&I2C_buf1,FFX_CONFIGURE_D,1,FFX_I2C_ADDR); I2C_buf1&=0xF7; I2C_buf1+=(PostscalelinkFlag<<3); I2Cm_Tx(&I2C_buf1,FFX_CONFIGURE_D,1,FFX_I2C_ADDR); void STA381BWX_Bass(unsigned char basssetting) basssetting=basssetting+1;...
  • Page 60 Examples of code (TV SoC) AN3959 I2C_buf1+=(treblesetting<<4); I2Cm_Tx(&I2C_buf1,FFX_TONEBASS,1,FFX_I2C_ADDR); /* Write coefficient into the FFX controller using the IIC driver */ void STA381BWX_init(void) unsigned char I2C_buf1; I2C_buf1=STA381BWX_STMAP; I2Cm_Tx(&I2C_buf1,STA381BWX_MAPSEL,1,FFX_I2C_ADDR); /* the master clock select, 256fs, fault detect enable */ I2C_buf1=0x63; I2Cm_Tx(&I2C_buf1,FFX_CONFIGURE_A,1,FFX_I2C_ADDR); /* the serial input format select, I2s format, MSB first*/ I2C_buf1=0x80;...
  • Page 61 AN3959 Examples of code (TV SoC) /* Switching frequency determined by AMAM setting and set the crossover as 260Hz*/ // STA381BWX_CrossOver(STA381BWX_Cross_260Hz); /* flat mode EQ*/ // I2C_buf1=0x00; // I2C_sendbuf(1,&I2C_buf1,FFX_I2C_WRITE_ADD,FFX_AUTO3); /* channel1 no limit, tone and treble control enable*/ // I2C_buf1=0x00;...
  • Page 62 Examples of code (TV SoC) AN3959 /* Limiter2 attack=+4dB and rease threshold=-2dB*/ // I2C_buf1=0x9d; // I2Cm_Tx(&I2C_buf1,FFX_L2AR_THRESHOLD,1,FFX_I2C_ADDR); STA381BWX_OutputConfiguration(STA381BWX_2_0_HP_Config); STA381BWX_Poweronoff(1); STA381BWX_SetMasterVolume(0); STA381BWX_SetLeftVolume(0x60); STA381BWX_SetRightVolume(0x60); // STA381BWX_SetSubWooferVolume(0x60); return; 62/65 Doc ID 022081 Rev 3...

  • Page 63: Appendix A Mono Btl Schematic

    Appendix A Mono BTL schematic Figure 54. Mono BTL schematic +3V3 RESET SWPA6045S220MT OUT+ 100nF 100nF 0 ohm 0 ohm 100nF 100nF SWPA6045S220MT 100nF OUT- OUTPUT FILTER LRCKI OUT- BICKI MCLK VCC_REG MCLK VSS_REG AGNDPLL C3 2u2/10V OUT2B VREGFILT FFX4B GND2 FFX4B FFX4A...

  • Page 64: Revision History

    Revision history AN3959 Revision history Table 8. Document revision history Date Revision Changes 02-Sep-2011 Initial release. Updated Figure 2: Schematic-1 on page 7 11-Nov-2011 Added Appendix A: Mono BTL schematic on page 63 05-Dec-2011 Updated Section 8.1: FFX381X_Sample.h Section 8.2: FFX381X_Sample.C...
  • Page 65 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

Table of Contents