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HUAWEI MU509-65 HSDPA LGA Module
Hardware Guide
Figure 3-23 Circuit diagram of the interface of the PCM (MU509-65 is used as PCM
master)
3.9 General Purpose I/O Interface
The module provides 8 GPIO pins for customers to use for controlling signals which
are worked at 2.6 V CMOS logic levels. Customers can use AT command to control
the state of logic levels of eight channels GPIO output signal, see the
MU509-65 HSDPA LGA Module AT Command Interface
Table 3-13 Signals on the GPIO interface
Pin
Pad
Pin No.
Name
Type
44, 45,
46, 51,
55, 105,
GPIO
I/O
109 and
113
3.10 JTAG Interface
The MU509-65 module provides one JTAG (Joint Test Action Group) interface. It is
suggested that place the follow test points in the DTE board for debug and take ESD
Issue 01 (2016-04-08)
It is recommended that a TVS be used on the related interface, to prevent electrostatic
discharge and protect integrated circuit (IC) components.
Description
General
Purpose I/O
pin
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
Description of the Application Interfaces
Min.
Parameter
(V)
V
2.15
OH
V
0
OL
V
1.69
IH
–0.3
V
IL
HUAWEI
Specification.
Typ.
Max.
Comments
(V)
(V)
The
2.6
2.6
function of
-
0.45
these pins
has not
2.6
2.9
been
defined.
-
0.91
41
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