Furuno FAX-30 Service Manual page 11

MAIN board (08P3218)
MAIN board consists of CPU, NET and PWR circuits.
CPU circuit
CPU consists of 32-bit CPU&DSP with a built-in Ethernet controller, 24-bit CODEC (AD
converter), Flash ROM and SDRAM.
The main function of CPU&DSP (U18) is as follows.
1) Filtering of received signal (DSP)
2) Demodulation of FAX data (DSP)
3) Demodulation of NAVTEX data (DSP)
4) Communication with NAVNET or PC (CPU)
5) Processing position data for auto NAVTEX reception (CPU)
6) Setting the receiving frequency for RCV circuit (CPU)
FAX signal (16.29 kHz) and NAVTEX signal are AD-converted by the CODEC and sent to
CPU&DSP. Flash ROM memorizes the system program and the image for backup. SDRAM
memorizes FAX image.
or
Fig.2 Block Diagram of CPU Circuit
Chapter 2 Circuit Description
(Using
16 bit)
3