Ic Block Diagram & Description - Sanyo DC-F320 Service Manual

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SIGNAL PROCESSOR)
Ground this pin through a capacitor when
decreasing the focus servo high-frequency gain.
1 3
d r i v e o u t p u t .
14
1 5
Setting pin fo lr Focus search, Tracking jump and
17
Sled kick cur
19 1
CLK
inoutfrom
DATA
21
Serial data input from CPU.
XRST
Reset input; resets at Low.
0
Track number count signal output.
0
Outputs FZC, DFCT, TZC, Gain, BAL, and
24
SENS
others according to the command from CPU.
FOK
0
Focus OK comparator output.
lC497 NJM7805FA I KIA7805PI
All manuals and user guides at all-guides.com
CPU.
OUTPUT PASS
No. I PIN NAME I VO j
Input pin for the DEFECT bottom hold output
c c 2
capacitance-coupled.
DEFECT bottom hold output.
27
cc1
Connection pin for DEFECT bottom hold
CB
capacitor.
Connection pin for MIRR hold capacitor. MIRR
29
comparator non-inverted input.
input pin for the RF summing amplifier output
capacitance-coupled.
RF summing amplifier output. Eye pattern check
31
RF summing amplifier inverted input. The RF
I
amplifier gain is determined by the resistance
connected between this pin and RF0 pin.
33
LD
0
34 I
PHD
these pins to the photo diodes F and E.
I-V amplifier E gain adjustment. (When not using
El
40
automatic balance adjustment.)
Ground
41
VEE
Tracking error amplifier output. E-F signal
42
TEO
Comparator input for balance adjustment. (Input
from TEO through LPF.)
I
Tracking error input.
44
TEI
I
Window comparator input for ATSC detection.
45
ATSC
Tracking zero-cross comparator input.
46
Capacitor connection pin for defect time
TDFCT
I
47
0
VC
IC231 LA1 832ML
Function
Power Controller) amplifier input.
I

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