Table of Contents
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Chassis Ground
25
Loop 1 HDSL Tip (Wire-Wrap)
26
Loop 1 HDSL Ring (Wire-Wrap)
27
28
29
30
31
32
33
Loop 2 HDSL Tip (Wire-Wrap)
34
Loop 2 HDSL Ring (Wire-Wrap)
35
36
37
38
39
40
41
DSX-1 Rx Tip (Wire-Wrap)
42
DSX-1 Rx Ring (Wire-Wrap)
43
44
45
46
47
48
DSX-1 Tx Tip (Wire-Wrap)
49
DSX-1 Tx Ring (Wire-Wrap)
50
Figure 3. HTU-C M Edge Connector Wiring
2B1Q
SPAN POWER
REGULATOR
HDSL
Figure 4. HTU-C M Span Powering Diagram
6
-48 RET
Fuse Alarm
-48V(1)
Input to HTU-C
Input to HTU-C
-48 RET
Output from HTU-C
Output from HTU-C
T (26)
LOOP 1
R (27)
SPAN CURRENT
T1 (34)
LOOP 2
R1 (35)
Section 61246001L2-5, Issue 2
splitting jacks provide an intrusive, signal interrupting
access to the line. This permits parameters to be
measured such as loop resistance, background noise
level, insertion loss, etc. It is very important to know
the direction of the access provided by a metallic
splitting jack.
Figure 5 illustrates the complete Bantam jack
arrangement and details for specific jacks.
T
DSX-1
R
DSX-1
MON
RX
EQ
RX
EQ
TX
DSX-1
MON
TX
T1
DSX-1
R1
Figure 5. HTU-C M Bantam Jack Arrangement
HTU-C M Loopbacks
The HTU-C M responds to two different loopback
activation processes. First, loopback may be activated
using the craft interface. The Loopback Options
Screen which provides for the HTU-C M, HTU-R, and
HRE loopbacks will be described in subsection 5.
Secondly, the HTU-C M responds to the industry
defacto standard for HDSL loopbacks. A detailed
description of these loopback sequences is given in
Appendix A.
The loopback condition imposed in both cases is a
logic level loopback at the point within the HTU-C M
where the DSX-1 signal passes into the HDSL
modulators. Figure 6 depicts all of the loopback
locations possible with ADTRAN HDSL equipment.
HTU-C
HDSL
HDSL
LOOP 1
LOOP 1
HTU-C
LOOP DC
DATA
POWER SOURCE
PUMP
HDSL
HDSL
LOOP 2
LOOP 2
61246001L2-5B
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Table of Contents
Troubleshooting
