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Freescale Semiconductor, Inc.
Daughter Card Connectors
The Serial Transmit Frame Sync pin, STFS, is programmed to control the codec's Frame
Sync signal, FSYNC. FSYNC is sampled by SCLK, with a rising edge indicating a new
frame is about to start. The FSYNC frequency is always the system's sample rate. It may
be an input to the codec, or it may be an output from the codec in data mode.
The basic codec digital connections are shown in
Figure
2-11.
The codec's MODE is set by the three MODE selection resistors, R96-R98. In the factory
default setting of MODE 4, the codec is set to be the Master of the SPI bus with its data
word set at 32 bits per frame; i.e., a 16-bit Left channel and a 16-bit Right channel. The
sample rate is selected on Sample Rate Selector switch S4; reference
Table 2-7
for
selection options. Codec control information is sent over a separate serial port using: PD1
as the Control Chip Select signal, CCS; PD2 as the Control Data Input signal, CDIN; and
PD3 as the Control Clock signal, CCLK.
2.13 Daughter Card Connectors
The EVM board contains two daughter card expansion connectors. One connector, J1,
contains the hybrid controller's external memory bus signals. The other connector, J2,
contains the device's peripheral port signals.
2.13.1 Memory Daughter Card Expansion Connector
The hybrid controller's external memory bus signals are connected to the Memory
Daughter Card Expansion connector, J1.
shows the port signal to pin
Table 2-8
assignments.
MOTOROLA
Technical Summary
2-15
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