Block Diagrams - National Instruments PCIe-6593 Getting Started Manual

Table 4. Available Pins on the QSFP+ Connectors (Continued)
Pin Symbol
32 GND
33 Tx3p
34 Tx3n
35 GND
36 Tx1p
37 Tx1n
38 GND

Block Diagrams

+5 V
+1.8 V
+12 V
10 | ni.com | PCIe-6593 Getting Started Guide
Ground
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground
Transmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground
Figure 6. FPGA Carrier Block Diagram
Flash
GPIO
MGTs
Configuration, GPIO
MGTs
Module Clocking
Synchronization
DRAM Bank 0
(2 GB)
Reference Clock
Name/Description
Power Supplies
+12 V
Gen3 x8 PCIe
FPGA
Clk 100
Clk 10
DRAM Bank 1
(2 GB)
+12 V, +3.3 V
Triggers