Haier L37V6-A8K Service Manual page 57

+3.3V_AVDD 3.3V_AVDD
Close to respective power Pins
1 2
FB14 C53 C54 C55 C56 C57 C58 C59 C60 C61
22uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
+3.3V_DVDD 3.3V_DVDD
Close to respective power Pins
Close to respective power Pins
1 2
FB15 C67 C68 C69 C70 C71 C72 C73 C74
22uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
+1.8V_DVDD CVDD_1.8
Close to respective power Pins
1 2
FB16 C78 C79 C80 C81 C82 C83 C84
FB0805
22uF 100nF 100nF 100nF 100nF 100nF 100nF
AVDD_1.8
+1.8V_AVDD
Close to respective power Pins
1 2
FB17 C90 C91 C92 C93 C94 C95 C96
22uF 100nF 100nF 100nF 100nF 100nF 220pF
BootStrap Signals
RMADDR[6:0] For I2C address [6:0] to JTAG bridge
Host I/F, to determine device address.
RMADDR[12:7] User_Bits[5:0] for configuration setting
OP_MODE[1:0]:
00 = Normal. UART in 186 on system pins.
01 = I2C to JTAG bridge.
RMADDR[14:13] 10 = JTAG port, 5 wires
11 = External parallel control bus using
ROM Addr/Data
SPI_EN: 0 = parallel ROM I/F. 1 = SPI
RMADDR15 serial ROM and Cache control
Initial state of OCM ROM: R73
0 = internal ROM on, and mapped to top
32K of OCM and OCM boot will be from 47R
internal ROM codes.
RMADDR16
1 = Internal ROM off. The external ROM
mapped to entire upper 512K of OCM
address. OCM boot from external ROM
code.
OSC_SEL: 0 = Xtal and internal oscillator.
RMADDR17
1 = TTL oscillator (on TCLK pin)
BOOTSTRAP OPTIONS SELECT
(NOT POPULATED SHOULD BE
HARD WIRED)
+5V_5221
JP4
MCSCL 10K_NC
MCSCL 1,2,8,9,11
3
MCSDA 10K_NC
MCSDA 1,2,8,9,11
2
10K_NC
1
10K_NC
10K_NC
CONN3_250MM
10K_NC
10K_NC
10K_NC
10K_NC
+5V_5221
10K_NC
10K_NC
10K_NC
10K
10K_NC
10K_NC
10K_NC
10K_NC
10K_NC
C62 C63 C64 C65 C66
100nF 100nF 100nF 100nF 220pF
C75 C76 C77
100nF 100nF 220pF
C85 C86 C87
100nF 220pF 220pF
100R R311 G_UART_DI
DDC_SCL_VGA 0 R312 UART_DI
C97 C98 100R R313 G_UART_DO
DDC_SDA_VGA_1 0 R314 UART_DO
220pF 100nF
0R/OP R70
1,8,9,11 RESETn
3 DDC_SCL_VGA
3 DDC_SDA_VGA_1
R71
1 DDC_SCL_DVI
0R SW1
1 DDC_SDA_DVI
SW PUSHBUTTON
3
C100
10 SOG
100nF
3
3
10nF C104 BLUE-
3 AHSYNC
10nF C105 GREEN-
3
10nF C106 RED-
1 RX2+
1 RX2-
1 RX1+
R74 R75
1 RX1-
1 RX0+
47R 47R
1 RX0-
1 RXC+
1 RXC-
3.3V_AVDD
SELECT ONE
3.3V_DVDD FB27 FB
1 2
+5V_5221 FB28 FB/OP
1 2
SOCKET:
+5V_5221
IC51-2084-1052
R409
10K
U15
C110
100nF
R89 RMADDR0
R91 RMADDR1 RMADDR17 30 32
NC/A17 VCC
R93 RMADDR2 RMADDR16 2
A16
R95 RMADDR3 RMADDR15 3 24
A15 OE
R96 RMADDR4 RMADDR14 29 31
A14 WE
R98 RMADDR5 RMADDR13 28
A13
R99 RMADDR6 RMADDR12 4 22
A12 CE
R100 RMADDR7 RMADDR11 25
A11
R101 RMADDR8 RMADDR10 23
A10
RMADDR9 26
A9
RMADDR8 27 21 RMDATA7
A8 DQ7
RMADDR7 5 20 RMDATA6
A7 DQ6
RMADDR6 6 19 RMDATA5
A6 DQ5
RMADDR5 7 18 RMDATA4
A5 DQ4
RMADDR4 8 17 RMDATA3
A4 DQ3
RMADDR3 9 15 RMDATA2
A3 DQ2
RMADDR2 10 14 RMDATA1
A2 DQ1
RMADDR1 11 13 RMDATA0
A1 DQ0
RMADDR0 12
A0
R103 RMADDR9 RMDATA[0..7]
R104 RMADDR10 1
NC
R105 RMADDR11 16
GND
R106 RMADDR12
R107 RMADDR13 AT49F020-70JC
R108 RMADDR14
R109 RMADDR15 32-Pin PLCC Socket
R110 RMADDR16
R111 RMADDR17
3.3V_DVDD
3.3V_DVDD
U14
3.3V_AVDD
11
AVDD_OUT_LV_E_33
24
AVDD_OUT_LV_E_33
26
AVDD_LV_33
27
AVDD_OUT_LV_O_33
40
AVDD_OUT_LV_O_33
113
AVDD_IMB_33
120
AVDD_RX2_33
125
AVDD_RX1_33
130 3.3V_A
AVDD_RX0_33
134
AVDD_RXC_33
141
AVDD_BLUE_33
145
AVDD_GREEN_33
150
AVDD_RED_33
+5V_5221 154
AVDD_ADC_33
172
LBADC_VDD_33
171
GPROBE
AVDD_RPLL_33
12
DEBUG
AVSS_OUT_LV_E
23
AVSS_OUT_LV_E
25
PORT
AVSS_LV
28
AVSS_OUT_LV_O
39
AVSS_OUT_LV_O
115
AGND_IMB
117
AGND_RX2
122 AGND
4 AGND_RX1
3.3V_AVDD 127
3 AGND_RX0
131
2 AGND_RXC
144
1 AGND_BLUE
149
AGND_GREEN
C88 C89 153
CN8
AGND_RED
156
RS232
AGND_ADC
15pF 15pF 168
AGND_RPLL
177
LBADC_GND
X1 136
GND_RXPLL
14.318MHz
TCLK 170
TCLK
XTAL 169
XTAL
71
HOST_SCL/UART_DI
72
HOST_SDA/UART_DO
77
DDC_SCL_VGA
78
DDC_SDA_VGA
DDC_SCL_DVI 79
DDC_SCL_DVI
DDC_SDA_DVI 80
DDC_SDA_DVI
178
RESETn
10nF C99 BLUE+ 142
BAIN BLUE+
R325 C101 BLUE- 143
BLUE-
0R/OP 10nF SOG_MCSS 146
SOG_MCSS
C102 GREEN+ 147
GAIN GREEN+
10nF GREEN- 148
GREEN-
C103 RED+ 151
RAIN RED+
10nF RED- 152
RED-
VGAHS 181
HSYNC
VGAVS 182
AVSYNC VSYNC
155
ADC_TEST
RX2+ 118
RX2+
RX2- 119
RX2-
RX1+ 123
RX1+
RX1- 124
RX1-
RX0+ 128
RX0+
RX0- 129
RX0-
RXC+ 132
RXC+
RXC- 133
RXC-
138
CLKOUT
R80 270 114
REXT
R238 3.3K RMADDR17 183
ROM_ADDR17
RMADDR16 184
ROM_ADDR16
RMADDR15 185
ROM_ADDR15
RMADDR14 186
ROM_ADDR14
RMADDR13 187
ROM_ADDR13
RMADDR12 188
ROM_ADDR12
RMADDR11 189
ROM_ADDR11
RMADDR10 192
ROM_ADDR10
RMADDR9 193
ROM_ADDR9
RMADDR8 194
ROM_ADDR8
RMADDR7 195
ROM_ADDR7
RMADDR6 196
ROM_ADDR6
RMADDR5 197
ROM_ADDR5
RMADDR4 198
ROM_ADDR4
RMADDR3 199
ROM_ADDR3
RMDATA[0..7] RMADDR2 200
ROM_ADDR2
RMADDR1 201
ROM_ADDR1
RMADDR0 202
ROM_ADDR0
RMDATA7 203
ROM_DATA7
R87 R88 RMDATA6 204
ROM_DATA6
10K 10K RMDATA5 207
ROM_DATA5
J5 RMDATA4 208
ROM_DATA4
JUMPER
RMDATA3 1
ROM_DATA3
RMDATA2 2
ROM_DATA2
RMDATA1 3
ROM_DATA1
RMDATA0 4
ROM_DATA0
ROM_OEn 5
ROM_OEn
ROM_WEn 6
ROM_WEn
ROM_CSn 7
ROM_CSn
0R/OP R328
gm5221
R102 PQFP208
10K
100R R359
1 AS_1
100R R360 R90
1 AS_2
100R R361
1 AS_3
1 VS1
8 MP3_GPIO
C113 R84
470K
100nF
- 57 -
AVDD_1.8
CVDD_1.8
CVDD_1.8
LV_E[0..9] 4,5
10
VCO_LV
13 LV_E9
CH3P_LV_E(PD0/ER0)
14 LV_E8
CH3N_LV_E(PD1/ER1)
15 LV_E7
CLKP_LV_E(PD2/ER2)
16 LV_E6
CLKN_LV_E(PD3/ER3)
17 LV_E5
CH2P_LV_E(PD4/ER4)
18 LV_E4
CH2N_LV_E(PD5/ER5)
19 LV_E3
CH1P_LV_E(PD6/ER6)
20 LV_E2
CH1N_LV_E(PD7/ER7)
21 LV_E1
CH0P_LV_E(PD8/EG0)
22 LV_E0
CH0N_LV_E(PD9/EG1)
LV_O[0..9] 4,5
29 LV_O9
CH3P_LV_O(PD10/EG2)
30 LV_O8
CH3N_LV_O(PD11/EG3)
31 LV_O7
CLKP_LV_O(PD12/EG4)
32 LV_O6
CLKN_LV_O(PD13/EG5)
33 LV_O5
CH2P_LV_O(PD14/EG6)
34 LV_O4
CH2N_LV_O(PD15/EG7)
35 LV_O3
CH1P_LV_O(PD16/EB0)
36 LV_O2
CH1N_LV_O(PD17/EB1)
37 LV_O1
CH0P_LV_O(PD18/EB2)
38 LV_O0
CH0N_LV_O(PD19/EB3)
PD[20..23] 5
43 PD20
PD20/EB4
44 PD21
PD21/EB5
45 PD22
PD22/EB6
46 PD23
PD23/EB7
+5V ENBKL
4 ENBKL
56
+5V
PD24/OR0
57 BRI
4 BRI
PD25/OR1
58 R336
5 DHS
PD26/OR2
59 4.7K/OP
5 DVS
PD27/OR3
60
+5V
PD28/OR4
61
PD29/OR5
62
PD30/OR6
63
PD31/OR7
64 R337
PD32/OG0
65 0R
PD33/OG1
66
PD37/OG5
+5V_5221
47 DEN
DEN DEN 5
48 DHS
DHS DHS 5
49 DVS
DVS DVS 5
55 DCLK
DCLK DCLK 5
R234
R236
67 PPWR 4.7K
4.7K
PPWR PPWR 4
68 PBIAS
PBIAS PBIAS 4
3.3K/OP R72
81 GPIO0
GPIO0
82 GPIO1
VGACON 3
GPIO1
83
GPIO2
84 100R R326
GPIO3 LED 2
85 SoftReset
STBY 6
GPIO4
88 100R R47
STBY_34XY
GPIO5
89
GPIO6
90 100R R327
IR_IN
GPIO7/IRQin
91 C107 100pF
GPIO8/IRQout
92 SCL 0R R76
MCSCL_EE
GPIO9/SCL
93 SDA 0R R77
MCSDA_EE
GPIO10/SDA
98 4.7K R78
PWM0 4
PWM0/GPIO11
99 PWM1 4.7K R79
PWM1/GPIO12
100
PWM2/GPIO13
101 C108 C109
5VAON 6
PWM3/GPIO14
69 47pF 47pF +5V_5221
VBI_INTR 9
STI_TM1/GPIO15
167
VBUFC_RPLL
135
VBUFC_DVI
R247
70
4.7K
STI_TM2
206
CRVSS
191
CRVSS
180
CRVSS
140
CRVSS
97 R83 100R/OP
CRVSS STBY_AMP
94
CRVSS
76 100 R48
CRVSS WP
74
CRVSS
51
CRVSS
42 3.3V_AVDD
CRVSS
8
CRVSS
87
CRVSS
165 R85 R86
GND_RPLL
163 470K 470K_NC
GND1_ADC
173 LBADC_IN1 R133
LBADC_IN1
174 LBADC_IN2 100 R92 33K
LBADC_IN2
175 LBADC_IN3 R94
LBADC_IN3
176 33K
LBADC_RETURN
C140 C111 C112 R137 R97 ADCIN:
12K 12K
2.53–3.2V = SCART
100nF_SC 100nF 100nF
1.33–2.13V = SCART
0–0.54V = SCART接口无信号
R138 0R
100R_SC
KEYBOARD INPUT
ADC_IN1 2
TO LBW ADC
T_STATE 11
TEMP_DETECT 6
Route (LBADC_IN1, LBADC_RET) and
(LBADC_IN2, LBADC_RET) as differential
tracks close to each other and ground the
return track of each pair very close to the
3.3V_AVDD
5221 and ground pin
RaisingSun Co.Ltd
Title
RS LCD TV
Size Document Number
C 5221
Date: Friday, April 22, 2005 Sheet
TJC3-10A
1
2
3
4
5
6
7
8
9
10
CN9
R235
4.7K
VGA_TV_SW 3
YUV_TV_SW 10
1
MUTE 1
2,8
R237
2
4.7K
2
+5V_5221
1
2
Scart_Signal_1 1
ADC_IN2 2
Scart_Signal_2 1
接口有 ： 信号
4 3
接口有 ： 信号
16 9
Rev
V0.1
7 of 12