2-3. Self Test Circuit
When the signal cable is disconnected from the video card/computer, pin @ of CN-IN and pin @ of IC851 (CPU)
are set High. Then H sync (pin a), V sync (pin @) and video (pin 0) compose the CPU generated self test
pattern.
N
CN-IN
L
SELF ID
B D7i5B
4
CPU
(5)
(Fig 2-3-l) Self Test Circuit
51
Need help?
Do you have a question about the MultiSync 4FGe and is the answer not in the manual?
Questions and answers