Kurzweil CUP2 Service Manual page 72

CUP2 Service Manual
5
VCC33
C52 C52 C53 C53 C54 C54 C55 C55 C56 C56 C57 C57 C58 C58 C59 C59 C60 C60
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D
sh.1,3,4,5 CPU_A_[22:0]
CPU_A_16 AF16
A_16
CPU_A_15 AE15
A_15
CPU_A_14 AF15
A_14
CPU_A_13 AE14
A_13
CPU_A_12 AF14
A_12
CPU_A_11 AF13
A_11
CPU_A_10 AE13
A_10
CPU_A_9 AF12
A_9
CPU_A_8 AE12
A_8
AF11
CPU_A_7
A_7
CPU_A_6 AE11
A_6
CPU_A_5 AE2
A_5
AF1
CPU_A_4
A_4
CPU_A_3 AE1
A_3
CPU_A_2 AD2
A_2
CPU_A_1 AD1
A_1
CPU_A_0 AC2
A_0
sh.1,3,4,5 CPU_D_[31:0]
CPU_D_31 M2
DHI_15
CPU_D_30 M1
DHI_14
CPU_D_29 L1
DHI_13
L2
CPU_D_28
DHI_12
CPU_D_27 K1
DHI_11
CPU_D_26 K2
DHI_10
CPU_D_25 J1
DHI_9
CPU_D_24 J2
DHI_8
CPU_D_23 H1
DHI_7
CPU_D_22 H2
DHI_6
CPU_D_21 G1
DHI_5
CPU_D_20 G2
DHI_4
CPU_D_19 F1
DHI_3
CPU_D_18 F2
DHI_2
CPU_D_17 E1
C
DHI_1
CPU_D_16 E2
DHI_0
CPU_D_15 Y2
DLO_15
CPU_D_14 Y1
DLO_14
CPU_D_13 W2
DLO_13
CPU_D_12 W1
DLO_12
CPU_D_11 V2
DLO_11
CPU_D_10 V1
DLO_10
CPU_D_9 U2
DLO_9
CPU_D_8 U1
DLO_8
CPU_D_7 T2
DLO_7
CPU_D_6 T1
DLO_6
R2
CPU_D_5
DLO_5
CPU_D_4 R1
DLO_4
CPU_D_3 P2
DLO_3
CPU_D_2 P1
DLO_2
CPU_D_1 N2
DLO_1
CPU_D_0 N1
DLO_0
AA1
sh.1,5 MARA_CS_L CE_L
AC1
sh.3 MARA_WR_L WR_L
AB2
sh.1,3,5 CPU_WAIT_L
READY/DTACK_L
AB1
sh.1,5 M1_DREQ_L DREQ_L
AA2
sh.1,5 M1_DACK_L
DACK_L
R102 R102
sh.1 M1_SDOUT_4
C93 C93 AF20
SD_OUT_7
0.1uF 0.1uF AE19
220 220 SD_OUT_6
AF19
sh.4 M1_SD_OUT_[3:0] SD_OUT_5
M1_SD_OUT_4 AE18
SD_OUT_4
M1_SD_OUT_3 AF18
SD_OUT_3
M1_SD_OUT_2 AE17
SD_OUT_2
AF17
M1_SD_OUT_1
SD_OUT_1
R103 R103 VCC33 M1_SD_OUT_0 AE16
SD_OUT_0
110 110
B
R22 R22 AD25
SD_IN_7
AE26
SD_IN_6
10K 10K AE25
SD_IN_5
AF26
SD_IN_4
AE24
SD_IN_3
AF25
SD_IN_2
R23 R23 AF24
SD_IN_1
AE23
M1_SD_IN_0
SD_IN_0
10K 10K
AE20
I8S_SCLK
AF21
I8S_SYNC
AE21
I2S_SCLK
sh.4 M1_I2S_BCLK
AF22
sh.4 M1_I2S_LRCK I2S_SYNC
AE22
LJ_SCLK
AF23
LJ_SYNC
AB26
SMOOCH_OUT_3
AB25
SMOOCH_OUT_2
VCC33 AC26
SMOOCH_OUT_1
AC25
SMOOCH_OUT_0
R26 R26
M1_SMCH_IN Y26
SMOOCH_IN_3
DNS DNS Y25
SMOOCH_IN_2
TP1 TP1 10K 10K AA26
SMOOCH_IN_1
HEADER_POST HEADER_POST 1 MARA1_GTOP AA25
SMOOCH_IN_0
AF10
GTOP
VCC18
R33 R33
MARA1_VDDAN AE4
VDDAN
DNS DNS
10 10
C100 C100 C98 C98 C99 C99 C101 C101 AF3
VSSAN
+ +
10uf 10uf 0.1uF 0.1uF 0.1uF 0.1uF AF4
PLL_BYPASS
22uF 22uF AE5
PLL_TST_1
AF5
PLL_TST_0
AE10
A
TST_CLK_OUT
AE9
CLK
AE8
REFCLK_OUT
sh.3 M1_CLK12_288_IN
AF6
RESET_L
DNS DNS
M1_REFCLK_OUT
R34 R34 22 22
sh.3,5 DSP_RESET_L
5
7- 4
4
VCC33 VCC25
C61 C61 C62 C62 C63 C63 + + + + + + C67 C67 C68 C68 C69 C69
C64 C64 C65 C65 C66 C66
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 100uF 100uF 22uF 22uF 22uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VCC33
cpu address cpu address
cpu data cpu data
cpu control cpu control
dma dma
standard audio standard audio
hi speed audio hi speed audio
pll pll
system system
4
3
MARA 1 DECOUPLING CAPS
VCC25
C76 C76
C70 C70 C71 C71 C72 C72 C73 C73 C74 C74 C75 C75 + + C78 C78 C79 C79 C80 C80
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 100uF 100uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VCC18
MARA MARA
U5 U5
3
2
L6 L6
VCC25 VCC18
C81 C81 600 OHM @ 100MHz 600 OHM @ 100MHz C82 C82 C83 C83 C84 C84 C85 C85 C86 C86 C87 C87 C88 C88 C89 C89
10uf 10uf 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
L7 L7
VCC18_ISO_M1
C94 C94 C95 C95 C96 C96 C97 C97 600 OHM @ 100MHz 600 OHM @ 100MHz
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uf 10uf
rom address rom address
B20 ROM_A_26
ROM_A_26
A21 ROM_A_25
ROM_A_25
B21 ROM_A_24
ROM_A_24
A22 ROM_A_23
ROM_A_23
B22 ROM_A_22
ROM_A_22
A23 ROM_A_21
ROM_A_21
B23 ROM_A_20
ROM_A_20
A24 ROM_A_19
ROM_A_19
B24 ROM_A_18
ROM_A_18
A25
ROM_A_17
ROM_A_17
B25 ROM_A_16
ROM_A_16
A26 ROM_A_15
ROM_A_15
B26
ROM_A_14
ROM_A_14
C25 ROM_A_13
ROM_A_13
C26 ROM_A_12
ROM_A_12
D25 ROM_A_11
ROM_A_11
D26 ROM_A_10
ROM_A_10
E25 ROM_A_9
ROM_A_9
E26 ROM_A_8
ROM_A_8
F25 ROM_A_7
ROM_A_7
F26 ROM_A_6
ROM_A_6
G25 ROM_A_5
ROM_A_5
G26
ROM_A_4
ROM_A_4
H25 ROM_A_3
ROM_A_3
H26 ROM_A_2
ROM_A_2
J25 ROM_A_1
ROM_A_1
J26 ROM_A_0
ROM_A_0
rom data rom data
M25 ROM_D_15
ROM_D_15
M26 ROM_D_14
ROM_D_14
N25 ROM_D_13
ROM_D_13
N26 ROM_D_12
ROM_D_12
P25 ROM_D_11
ROM_D_11
P26 ROM_D_10
ROM_D_10
R26 ROM_D_9
ROM_D_9
R25 ROM_D_8
ROM_D_8
T26 ROM_D_7
ROM_D_7
T25 ROM_D_6
ROM_D_6
U26 ROM_D_5
ROM_D_5
U25 ROM_D_4
CFG_4/ROM_D_4
V26 ROM_D_3
CFG_3/ROM_D_3
V25 ROM_D_2
CFG_2/ROM_D_2
W26 ROM_D_1
CFG_1/ROM_D_1
W25 ROM_D_0
CFG_0/ROM_D_0
rom control rom control RN13 RN13
L25 1
ROM_WE_EVN_L
K26 2
ROM_CS_1/WE_ODD_L
L26 3
ROM_CS_0/QSA_EVN_L
K25 4
ROM_OE_L
22 22
ddr sdram address ddr sdram address
B11 DDR_BA_1
DDR_BA_1
A11 DDR_BA_0
DDR_BA_0
B12 DDR_A_12
DDR_A_12
A12 DDR_A_11
DDR_A_11
B13 DDR_A_10
DDR_A_10
A13 DDR_A_9
DDR_A_9
A14 DDR_A_8
DDR_A_8
B14 DDR_A_7
DDR_A_7
A15 DDR_A_6
DDR_A_6
B15 DDR_A_5
DDR_A_5
A16 DDR_A_4
DDR_A_4
B16 DDR_A_3
DDR_A_3
A17 DDR_A_2
DDR_A_2
B17 DDR_A_1
DDR_A_1
A18
DDR_A_0
DDR_A_0
ddr sdram data ddr sdram data
C1 DDR_D_15
DDR_D_15
C2 DDR_D_14
DDR_D_14
B1 DDR_D_13
DDR_D_13
B2 DDR_D_12
DDR_D_12
A1 DDR_D_11
DDR_D_11
B3 DDR_D_10
DDR_D_10
A2 DDR_D_9
DDR_D_9
A3
DDR_D_8
DDR_D_8
B6 DDR_D_7
DDR_D_7
A6 DDR_D_6
DDR_D_6
B7
DDR_D_5
DDR_D_5
A7 DDR_D_4
DDR_D_4
B8 DDR_D_3
DDR_D_3
A8 DDR_D_2
DDR_D_2
B9 DDR_D_1
DDR_D_1
A9 DDR_D_0
DDR_D_0
ddr sdram control ddr sdram control
B4
DDR_DQS_3
A4
DDR_DQS_2
B5
DDR_DQS_1
A5
DDR_DQS_0
A10
DDR_CAS_L
A20
DDR_RAS_L
B19
DDR_WE_L
A19
DDR_CLK_H
B18
DDR_CLK_L
B10
DDR_CKE
D2
VREF
jtag jtag
AE7
TDO
AF9
TDI
AF7
TCK
AE3
TMS
AF8 M1_TRST_L
TRST_L
internal scan internal scan
AE6 R11 R11
TEST_MODE
AF2
1.0K 1.0K
SCANENABLE
MARA MARA
2
1
VCC18 VCC18
C90 C90 C91 C91 + +
C92 C92
1uf 1uf 1uf 1uf 100uF 100uF
0805 0805 0805 0805
VCC18
D
ROM_A_[26:0] sh.4
ROM_D_[15:0] sh.4
C
VCC33
RN12 RN12
ROM_D_4 1 8
ROM_D_3 2 7
ROM_D_2 3 6
ROM_D_0 4 5
10K 10K
M1_ROM_D_1 is Don't Care on Power Up
8
7
ROM_CS1_L sh.4
6
ROM_CS0_L sh.4
5
ROM_OE_L sh.4
DDR_BA_[1:0] sh.3
DDR_A_[12:0] sh.3
DDR_D_[15:0] sh.3
B
DDR_DQS_2 sh.3
DDR_DQS_0 sh.3
DDR_CAS_L sh.3
DDR_RAS_L sh.3
DDR_WE_L sh.3
DDR_CLK_H sh.3
DDR_CLK_L sh.3
DDR_CKE sh.3
DDR_VREF sh.3
A
Young Chang R&D Institute
1432 Main St.
Waltham MA 02451
USA Copyright 2010 Young Chang Co., Ltd.
Reproduction without the express written consent of Young Chang Co., Ltd. is prohibited.
Title RP2A ENGINE BOARD - SP4x Configuration
MARA
Size By Document Number Rev
R. Folk 021402 DV2-A
Date: Friday, January 07, 2011 Sheet 2 of 5
1