AOpen AP5V User Manual page 57

This parameter controls the wait state between SDRAM row address, strobe
and SDRAM CAS signals.
This parameter controls the RAS# precharge, RAS# active-to-precharge time,
and refresh-to-RAS# active signal delay.
8-bit I/O Recovery Time (Sysclk)
This parameter allows you to set the response time of the 8-bit I/O devices
connected to your system. The settings range from
Disabled
.
16-bit I/O Recovery Time (Sysclk)
This parameter allows you to set the response time of the 16-bit I/O devices
connected to your system. The settings range from
Disable .
ISA Clock Divisor
This option specifies the ISA bus clock divisor.
PCICLK/4 and PCICLK/3
Peer Concurrency
Enable the parameter to allow the CPU to run secondary DRAM PCI master
cycles to target PCI peer devices. Select
Disabled
The default setting is
*
This parameter is nonconfigurable.
AMI BIOS Utility
SDRAM CAS# LATENCY
SDRAM RAS# TIMING *
.
Disabled
.
*
1-8 SYSCLK
and
1-4 SYSCLK d
and
The selections are
to hold the CPU bus.
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