Xilinx T1 User Manual page 23

Table 2: Zynq UltraScale+ RFSoC ZU21 Pin Map (cont'd)
Pin Number
A11
B14
C12
A10
G14
L11
H14
J14
H9
H12
G13
K11
H11
W7
Y7
W5
W9
W4
Y6
G7
W8
Y5
D9
C6
E8
E7
C9
F5
C7
E5
G9
M8
J9
K10
L8
L10
L6
J10
K6
UG1495 (v1.0) December 17, 2021
T1 Telco Accelerator Card User Guide
Signal Name
PL_DDR4_1_DQ11
PL_DDR4_1_DQ10
PL_DDR4_1_DQ13
PL_DDR4_1_DQ15
PL_DDR4_1_DQ34
PL_DDR4_1_DQ33
PL_DDR4_1_DQ36
PL_DDR4_1_DQ32
PL_DDR4_1_DQ31
PL_DDR4_1_DQ35
PL_DDR4_1_DQ38
PL_DDR4_1_DQ37
PL_DDR4_1_DQ39
PL_DDR4_1_DQ59
PL_DDR4_1_DQ63
PL_DDR4_1_DQ58
PL_DDR4_1_DQ61
PL_DDR4_1_DQ60
PL_DDR4_1_DQ62
PL_DDR4_1_DQ26
PL_DDR4_1_DQ57
PL_DDR4_1_DQ56
PL_DDR4_1_DQ2
PL_DDR4_1_DQ3
PL_DDR4_1_DQ4
PL_DDR4_1_DQ0
PL_DDR4_1_DQ6
PL_DDR4_1_DQ7
PL_DDR4_1_DQ1
PL_DDR4_1_DQ5
PL_DDR4_1_DQ27
PL_DDR4_1_DQ44
PL_DDR4_1_DQ47
PL_DDR4_1_DQ46
PL_DDR4_1_DQ42
PL_DDR4_1_DQ40
PL_DDR4_1_DQ45
PL_DDR4_1_DQ43
PL_DDR4_1_DQ41
Chapter 2: Pin Mapping
Interface
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
PL 72-bit DDR4
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