Xilinx T1 Installation Manual
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Xilinx T1 Installation Manual

Telco accelerator card
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T1 Telco Accelerator Card
Installation Guide
UG1518 (v1.0) December 17, 2021
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  • Page 1 T1 Telco Accelerator Card Installation Guide UG1518 (v1.0) December 17, 2021 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve...

  • Page 2: Table Of Contents

    Flashing the Images in QSPI Using flash_app............... 14 Chapter 5: T1 Skeleton Design ................16 T1 Skeleton Design on the ZU19 Zynq UltraScale+ MPSoC..........16 T1 Skeleton Design on the ZU21 Zynq UltraScale+ RFSoC........... 17 T1 Skeleton Design Package....................18 Chapter 6: Running the Tests .................20...
  • Page 3 VCCI Class A Statement......................45 Appendix C: Additional Resources and Legal Notices ......46 Xilinx Resources.........................46 Documentation Navigator and Design Hubs.................46 Revision History......................... 46 Please Read: Important Legal Notices................... 47 UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 4: Chapter 1: Introduction

    Chapter 1 Introduction This document provides hardware and software installation procedures for the T1 Telco accelerator card along with a guide to the T1 skeleton design. The skeleton design is created specifically for the 16 nm Zynq ® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices on the T1 card, and provides connections and software to validate the main interfaces of the board.

  • Page 5: Minimum System Requirements And Setup

    • 4G LTE and 5G NR inline acceleration of L1 functions (supporting 3GPP split option 7-2x) for up to 4TRX The T1 card turns a standard server into a virtual baseband unit with the performance, low latency, and power efficiency needed for O-RAN 5G deployments. The turnkey solution enables operators, system integrators, and OEMs to get to market quickly and to simplify the deployment of services at the edge.

  • Page 6: Configuring The Pcie Slot Bifurcation

    Chapter 1: Introduction Configuring the PCIe Slot Bifurcation Perform the following steps to enable bifurcation in the slot where the T1 card has been inserted. This is required for the T1 card to work properly. Note: These steps are for a single T1 card deployment.
  • Page 7 5. Select Integrated Devices. 6. In the menu that is displayed, scroll down until you get to Slot Bifurcation. It is on the second half of the page. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...
  • Page 8 7. Click the required slot to change bifurcation. 8. Click Default Bifurcation and select x8x8 or x8 Bifurcation. This enables the T1 card in the slot with the correct communication over the PCI. Click the Back button in the lower right hand side of the screen.
  • Page 9 12. Click the Finish button again. 13. When the system has rebooted, check to see if the T1 card has been detected using the lspci | grep Xilinx command. If the card has been detected, the response should look like the following figure.
  • Page 10 Chapter 1: Introduction UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 11: Chapter 2: Card Information And Installation

    • Put the card down only on an antistatic surface such as the bag supplied in your kit. • If you are returning the card to Xilinx product support, place it back in its antistatic bag immediately. Before You Begin IMPORTANT! The T1 Telco accelerator card is a delicate and sensitive electronic device and should be installed by a qualified technician only.

  • Page 12: Installing The Card

    Note: There is no auxiliary power connector on the T1 card. Note: There is also a USB JTAG connector that can be connected from the server to the T1 card. It can be used to program the flash. This is for development purposes and is not intended for use in a production setting.

  • Page 13: Chapter 3: Installing Additional Software

    The dpdk-kmods package is therefore included in the T1 card skeleton design package. • Application scripts This software is included in the T1 skeleton design package along with a script to ensure that the software is installed correctly. The package and the scripts are described in the...

  • Page 14: Chapter 4: T1 Factory Installed Image

    Chapter 4: T1 Factory Installed Image Chapter 4 T1 Factory Installed Image The T1 Telco accelerator card is preprogrammed with an image in the QSPIs on the card that consists of two separate designs that support the two Xilinx ®...
  • Page 15 Chapter 4: T1 Factory Installed Image 2. Execute ./rfsoc_flash_qspi.sh <RFSOC BOOT.BIN absolute file path> [<QSPI flash offset> [<PCIe BDF>]] inside the flash_app directory. 3. Wait until the message “Programmed boot image” appears. Flashing the SC Image Using the sc_flash Script 1.

  • Page 16: Chapter 5: T1 Skeleton Design

    Note: The T1 skeleton design is limited to working only in even-numbered PCIe slots. If you use an odd- numbered slot, designs can be loaded into the devices, but the tests described in...

  • Page 17: T1 Skeleton Design On The Zu21 Zynq Ultrascale+ Rfsoc

    Chapter 5: T1 Skeleton Design Figure 2: ZU19 Skeleton Design Connections T1 Skeleton Design on the ZU21 Zynq UltraScale+ RFSoC The design on the ZU21DR Zynq UltraScale+ RFSoC has Linux running on the PS Cortex-A53 processors and has connections from the PCIe Gen3 x8 from the host to the different parts of the ZU21.

  • Page 18: T1 Skeleton Design Package

    Figure 3: ZU21 Skeleton Design Connections T1 Skeleton Design Package The T1 card skeleton design package comes as a Git repository. The code is stored in different branches, with one separate branch for each supported DPDK version (18.11, 19.11, and 20.11).
  • Page 19 Chapter 5: T1 Skeleton Design The files are described below. • build.sh: This script downloads all packages from the Internet and applies Xilinx patches. • compile.sh: This script is used to compile the additional host software required to run the design.

  • Page 20: Chapter 6: Running The Tests

    Chapter 6: Running the Tests Chapter 6 Running the Tests The skeleton design has the following setup to test the T1 card. Figure 5: Test Setup Dell PowerEdge R740 Server Pktgen Application Pktgen Application Port 1 Port 2 QDMA Poll Mode Driver...

  • Page 21: 100G Internal Connection Between Zynq Ultrascale+ Mpsoc And Zynq Ultrascale+ Rfsoc

    Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC using the DPDK pktgen application. The Xilinx QDMA IP core is used for sending or receiving data to or from the host. All 4 x 25G lanes are mapped to queues 1,2,3, and 4 of the QDMA core respectively in the Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC devices.
  • Page 22 The expected results running the lanes 1, 2, 3, and 4 are similar. The result for L1 is shown below. Test Requirements The application TX and RX throughput should be in the range pf 25 Gb/s for both ports in the Pktgen application. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 23: X 25G External Sfp Test

    2 x 25G External SFP Test The two 25G MAC cores are instantiated in the FPGA. The SFP ports of the T1 card are connected using a 25G optical SFP cable. The FPGA reroutes the packets received in QDMA to the external SFP, and then routes them from the external SFP back to QDMA.
  • Page 24 • There should not be any packet loss; RX and TX counts should be identical. • There should be no mismatch in TX and RX packets. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 25: Zu19 Zynq Ultrascale+ Mpsoc Pcie Loopback Test

    8. When the test is complete, stop traffic with the command stop all and then quit the test. The expected results from running the Zynq UltraScale+ MPSoC PCIe loopback test are shown below. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...
  • Page 26 • There should not be any packet loss; RX and TX counts should be identical. • There should not be any mismatch in TX and RX packets. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 27: Zu21 Zynq Ultrascale+ Rfsoc Pcie Loopback Test

    8. When the test is complete, stop traffic with the command stop all and then quit the test. The expected results from running the Zynq UltraScale+ RFSoC PCIe loopback test are shown below. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...
  • Page 28 • There should not be any packet loss; RX and TX counts should be identical. • There should not be any mismatch in TX and RX packets. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 29: Ddr Read/Write Tests

    MPSoC RFSoC Xilinx ® T1 Telco Card X25235-033121 Test Procedure 1. Ensure the conditions in the Chapter 2: Card Information and Installation section have been met. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...
  • Page 30 4. Execute the test.sh script, with either mdt or rdt as argument, to launch the QDMA test application for the Zynq UltraScale+ MPSoC or the Zynq UltraScale+ RFSoC. 5. When the xilinx-app prompt comes up, initialize the port with the command port_init 0 1 0 1024 4096 within the test application.
  • Page 31 Chapter 6: Running the Tests Test Requirements • Contents of the text files for H2C and C2H should match after DMA transfers. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 32: Test Application Guide And Address Map

    The QMDA test application guide is available here. The address map used in the tests in this document is shown in the following figure. Figure 7: Address Map UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 33: Chapter 7: Next Steps

    If you are an application developer who wants to develop and deliver a customized solution on the T1 Telco accelerator card, the skeleton design described in this document is a starting point. You can also start a design from scratch using the development tools located at the...

  • Page 34: Chapter 8: Dependencies/Known Issues

    • The boot mode does not change from QSPI mode to JTAG mode when a JTAG cable is connected. • PCIe ® remove and rescan operations do not currently work for the T1 card, and might lead to the card malfunctioning. • QSPI flash programming works in Vivado ®...

  • Page 35: Appendix A: Programming The Devices Using Jtag

    The QSPI flash or the devices can also be programmed through JTAG using an ADK connector. The Xilinx tools must be installed on a computer and then connected to the T1 card through an ADK connector. An ADK connector is not part of the T1 card and must be obtained separately.
  • Page 36 To complete the setup, connect the ribbon cable to the ADK card, then connect the ADK card to a micro USB cable so that it can connect to a computer that can run the Xilinx tools. The full connection is shown below.
  • Page 37 USB cable going out the back of the server. This setup allows the USB to be connected to an external laptop running on the server. The Xilinx tools can be on the laptop or the server to program the devices on the T1 card.

  • Page 38: Flashing The Images To Zu19 Zynq Ultrascale+ Mpsoc Qspi Using Sdk

    The following describes using the how to use the Xilinx tools to program the QSPIs on the T1 card. Note: If you use this method, the Xilinx tools must be loaded on the server and it is necessary to connect an ADK connector for the programming using JTAG.
  • Page 39 Appendix A: Programming the Devices Using JTAG 1. Ensure that an ADK cable is connected between the ADK connector on the T1 card and the USB port on the host machine. The T1 card with an ADK connected is shown in...

  • Page 40: Flashing The Images To Zu21 Zynq Ultrascale+ Rfsoc Qspi Using Sdk

    (using the same steps but for the ZU21 instead of the ZU19). 1. Ensure that an ADK cable is connected between the ADK connector on the T1 card and the USB port on the host machine. The T1 with an ADK connected is shown in the previous section (outside of a server).

  • Page 41: Programming The Bitstreams Directly

    2. Perform a warm reboot on the host machine. 3. Program the bitstream using Vivado Hardware Manager as shown below for either the ZU21 or ZU19. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...
  • Page 42 GUI, you might also need to change the PCIe settings in the Console during the restart. 5. Perform a warm reboot on the host machine. UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 43: Appendix B: Regulatory Compliance Statements

    UL 62368-1, 2nd Edition, 2014-12-01, Information technology equipment – Safety, Part 1: General requirements CSA C22.2 No. 62368-1-14, 2nd Edition, 2014-12-01, Information Technology Equipment – Safety, Part 1: General Requirements UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 44: Emc Compliance

    Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at their own expense. CAUTION! If the device is changed or modified without permission from Xilinx, the user may void their authority to operate the equipment.

  • Page 45: Vcci Class A Statement

    Appendix B: Regulatory Compliance Statements VCCI Class A Statement UG1518 (v1.0) December 17, 2021 www.xilinx.com Send Feedback T1 Telco Accelerator Card Installation Guide...

  • Page 46: Appendix C: Additional Resources And Legal Notices

    • On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •...

  • Page 47: Please Read: Important Legal Notices

    IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...
  • Page 48 Appendix C: Additional Resources and Legal Notices Copyright © Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license.

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