Overview - Xilinx T1 User Manual

• x16 standard card form factor (FHHL), single slot (111.15 mm x 167.65 mm)
• Maintenance port for card maintenance and developer access using the DMB II Interface
(proprietary, requires Xilinx

Overview

The system hardware contains a single PCB assembly. The MNC2 card is built with a XCZU21DR
Zynq UltraScale+ RFSoC and a XCZU19EG Zynq UltraScale+ MPSoC. The connectivity includes
two 25G interfaces and one x16 Gen 3.0 PCIe interface. Each SoC acts as a Gen3.0 x8 endpoint
with respect to root complex. One DDR4 Memory controller is implemented inside the PL
section of both SoCs. A second set of DDR4 memory is interfaced to PS section of both SoCs.
One 100G transceiver is implemented on both SoCs for inter-SoC communication. A detailed
block diagram of the T1 card card is shown in the following figure.
QSPI Flash
Memory
DDR4, x16
8GB + ECC
DDR4, x16
4GB + ECC
Level
Translator
SFP28
25G
MAC
Level
Translator
SFP28
25G
MAC
PPS_IN_MPSOC
Clock MPSOC
PPS_IN
Buffer
PPS_IN_RFSOC
Clock
Synchronizer
PPS_OUT
UG1495 (v1.0) December 17, 2021
T1 Telco Accelerator Card User Guide
® DMB II kit)
Figure 3: Detailed T1 card Block Diagram
Zync UltraScale+
MPSoC
IO[0:7]
Configuration
XCZU19EG
SCK
Block
-L2FFVD1760E
CS
PS
DDR4
TCK
JTAG TMS
DDR4_1_A[0:16]
TDI
DDR4_1_BA[0:1]
TDO
DDR4_1_DM[0:4]
DDR4_1_DQ[0:39]
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
UART
DDR4_1_RST
DDR4 100G MAC0
MAC0_CLK_P/N
DDR4_0_A[0:16]
MAC0_TX_P/N[0:3]
DDR4_0_BA[0:1]
MAC0_RX_P/N[0:3]
DDR4_0_DM[0:8]
MAC0_RST
DDR4_0_DQ[0:71]
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST
Clock
I2C_0
I2C_0
25G MAC0
Reset
GT_RX_P/N
GT_RX_P/N
SFP0_REFCLK_RST
PCIe Hard
Block Gen3 x8
I2C_1
25G MAC1
GT_RX_P/N
GT_RX_P/N
SFP1_REFCLK_RST
RFSOC
Mini-USB
Conn
Zync UltraScale+
RFSoC
XCZU21DR
FTDI
-L2FSVD1156E
Chip
TCK
TMS JTAG
TDI
TDO
UART
100G MAC0
100G MAC
MAC0_CLK_P/N
MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]
MAC0_RST
EEPROM
Clock Generator Clock
I2C_0
I2C Level
Reset
Translator
Inlet Temp Outlet Temp
PCIe Hard
Sensor Sensor
Block Gen3 x8
I2C_0
MCU
I2C_1 I2C_2
FTDI
PSU
Chip
CLOCK
Buffer
PCIE_REFCLK_P/N
PCIE EDGE FINGER
Send Feedback
Chapter 1: Introduction
IO[0:7]
Configuration
QSPI Flash
SCK
Block
Memory
CS
PS
DDR4
DDR4_1_A[0:16]
DDR4_1_BA[0:1]
DDR4_1_DM[0:4]
DDR4, x16
DDR4_1_DQ[0:39]
8GB + ECC
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
DDR4_1_RST
DDR4
DDR4_0_A[0:16]
DDR4_0_BA[0:1]
DDR4_0_DM[0:8]
DDR4, x16
DDR4_0_DQ[0:71]
4GB + ECC
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST
PM
PCIE_12V
VCC_12V
OR
ATX_12V
Module
www.xilinx.com
VCC_0V72
VCC_0V85
VCC_0V9
VCC_1V2
VCC_1V8
VCC_3V3
X24621-092320
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