Asus AAEON BOXER-6839-CFL User Manual
  1. Manuals
  2. Brands
  3. Asus Manuals
  4. Desktop
  5. AAEON BOXER-6839-CFL
  6. User manual

Asus AAEON BOXER-6839-CFL User Manual

Fanless embedded box pc
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
BOXER-6839-CFL
Fanless Embedded Box PC
st
User's Manual 1
Ed
Last Updated: March 24, 2021

Advertisement

Table of Contents
loading

Related Manuals for Asus AAEON BOXER-6839-CFL

Summary of Contents for Asus AAEON BOXER-6839-CFL

  • Page 1 BOXER-6839-CFL Fanless Embedded Box PC User’s Manual 1 Last Updated: March 24, 2021...
  • Page 2 Copyright Notice This document is copyrighted, 2021. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other product name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel®, Pentium®, Celeron®, and Xeon® are registered trademarks of Intel ⚫ Corporation Intel Core™ is a trademark of Intel Corporation ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity BOXER-6839-CFL ⚫ Wallmount bracket ⚫ Screw Package ⚫ 3 Pin DC-In Power Connector ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯 醚(PBDE) (Pb) (Hg) (Cd) (Cr(VI)) (PBB) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 ○ ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 BOXER-6839-CFL Dimensions ................5 Jumpers and Connectors ..................8 List of Jumpers ......................9 2.3.1 Setting Jumpers ..................9 2.3.2 Auto Power Button Selection (AT/ATX Mode) (JP19) ......
  • Page 12 2.4.17 Mini Card Slot (Full-Sized) (PCIE1) ............31 2.4.18 Mini Card Slot with mSATA (Full Sized) (PCIE2) ......33 2.4.19 SATA PWR (PWR 1,2) ................36 2.4.20 SATA Port (SATA 3,4)................36 2.4.21 SIM Slot (SIM1) ..................37 CPU Installation..................... 38 Expansion Card Installation ................
  • Page 13 3.4.7.6 Serial Port 6 Configuration ........... 66 3.4.8 Advanced: Network Stack Configuration ........67 3.4.9 Advanced: Digital IO Port Configuration ......... 70 3.4.10 Advanced: Power Management ............71 Setup Submenu: Chipset ..................73 3.5.1 Chipset: System Agent (SA) Configuration ........74 3.5.2 Chipset: PCH-IO Configuration ............

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Intel® Xeon® E-2124G Intel® i9-9900T Intel® i7-9700TE Intel® i7-8700T Intel® i5-8500T Intel® i3-8100T Pentium® G5400T Celeron® G4900T C246 Chipset DDR4-2666 SO-DIMM slot x 2 System Memory Up to 64GB, ECC or Non-ECC Supported HDMI x 2 Display Interface 2.5”...
  • Page 16 System HDD LED x 1 Indicator System LED x 1 Windows® 10 64-bit OS Support Linux Ubuntu 20.04 Power Supply Power Requirement 3-pin Phoenix DC Input 10~35V Mechanical Mounting Wallmount Dimensions (W x H x D) 264mm x 156mm x 125mm Gross Weight 13.2 lbs.

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Boxer-6839-Cfl Dimensions

    BOXER-6839-CFL Dimensions Chapter 2 – Hardware Information...
  • Page 19 Chapter 2 – Hardware Information...
  • Page 20 Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Note: Board dimensions are 225mm x 151.5mm x 1.8mm Chapter 2 – Hardware Information...

  • Page 22: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the system’s jumpers that you can configure for your application. Label Function JP19 Auto-Power Button Selection (AT/ATX Mode) JP24 CMOS Control Selection (Clear CMOS) 2.3.1 Setting Jumpers The BOXER-6839-CFL comes with several jumpers which allow you to configure the system by either setting the jumper to “open”...

  • Page 23: Auto Power Button Selection (At/Atx Mode) (Jp19)

    2.3.2 Auto Power Button Selection (AT/ATX Mode) (JP19) ATX Mode (default) AT Mode/ Auto Power Disabled Auto Power Enabled Note: Disable Auto Power Button JP19 (1-2) requires user to use power button JP19 (1-2) to power on the system. 2.3.3 CMOS Control Selection (JP24) 1 2 3 Normal (Default)

  • Page 24: List Of Connectors

    List of Connectors Please refer to the table below for all of the system’s connectors that you can configure for your application Label Function BAT1 RTC Battery Phoenix Connector Power Input SPI flash port PCIe [x4] Slot CN14 LAN+USB3.2 Gen 1 x2 Connector CN15 LAN+USB3.2 Gen 1 x2 Connector CN18...

  • Page 25: Pheonix Connector Power Input (Cn2)

    Label Function PWR2 SATA PWR Connector SATA3 SATA3 SATA4 SATA4 SIM1 SIM Card Slot Power Button Reset Switch 2.4.1 Pheonix Connector Power Input (CN2) Signal Level Signal Signal Type +10V~+35V GND_EARTH Chapter 2 – Hardware Information...

  • Page 26: Spi Flash Port (Cn7)

    2.4.2 SPI Flash Port (CN7) Signal Signal Type Signal Level SPI_MISO SPI_CLK +3.3VSB +3.3V SPI_MOSI SPI_CS 2.4.3 PCIe [x4] Slot (CN8) Signal Level Signal Signal Type PRSNT1# +12V +V12S +12V +V12S PCIE_TXN5 DIFF PCIE_TXP5 DIFF PCIE_RXN5 DIFF PCIE_RXP5 DIFF Chapter 2 – Hardware Information...
  • Page 27 Signal Signal Type Signal Level +3.3V +V3.3S +3.3V +V3.3S PERST# PCIE_x4SLOT_CLK DIFF PCIE_x4SLOT_CLK# DIFF PCIE_RXP24 DIFF PCIE_RXN24 DIFF PCIE_RXP23 DIFF PCIE_RXN23 DIFF PCIE_RXP22 DIFF PCIE_RXP22 DIFF PCIE_RXP21 DIFF PCIE_RXN21 DIFF +12V +V12S +12V +V12S Chapter 2 – Hardware Information...
  • Page 28 Signal Signal Type Signal Level +12V +V12S SMB_CLK SMB_DATA +V3.3S +V3.3S 3.3Vaux +V3.3A WAKE# PCIE_TXP24 DIFF PCIE_TXN24 DIFF PRSNT PCIE_TXP23 DIFF PCIE_TXN23 DIFF PCIE_TXP22 DIFF PCIE_TXN22 DIFF PCIE_TXP21 DIFF PCIE_TXN21 DIFF Chapter 2 – Hardware Information...

  • Page 29: Lan (Rj-45) + Dual Usb3.2 Gen 1 (Cn14)

    Signal Signal Type Signal Level PRSNT 2.4.4 LAN (RJ-45) + Dual USB3.2 Gen 1 (CN14) Signal Level Signal Signal Type MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF Chapter 2 – Hardware Information...
  • Page 30 Signal Signal Type Signal Level +5VSB USB7_D- DIFF USB7_D+ DIFF USB7_SSRX− DIFF USB7_SSRX+ DIFF USB7_SSTX− DIFF USB7_SSTX+ DIFF +5VSB USB8_D- DIFF USB8_D+ DIFF USB8_SSRX− DIFF USB8_SSRX+ DIFF USB8_SSTX− DIFF USB8_SSTX+ DIFF Chapter 2 – Hardware Information...

  • Page 31: Lan (Rj-45) + Dual Usb3.2 Gen 1 (Cn15)

    2.4.5 LAN (RJ-45) + Dual USB3.2 Gen 1 (CN15) Signal Level Signal Signal Type MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF Signal Level Signal Signal Type +5VSB USB5_D- DIFF USB5_D+ DIFF USB5_SSRX−...

  • Page 32: Audio Connector (Cn18)

    Signal Signal Type Signal Level USB5_SSTX− DIFF USB5_SSTX+ DIFF +5VSB USB6_D- DIFF USB6_D+ DIFF USB6_SSRX− DIFF USB6_SSRX+ DIFF USB6_SSTX− DIFF USB6_SSTX+ DIFF 2.4.6 Audio Connector (CN18) Signal Signal Type Signal Level AUD_GND LOUT_L LOUT_R HP_DET_3 Chapter 2 – Hardware Information...

  • Page 33: Digital Io Port (Cn43)

    Signal Signal Type Signal Level HP_DET_4 MIC_L MIC_R HP_DET_1 HP_DET2 2.4.7 Digital IO Port (CN43) Signal Signal Type Signal Level DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 Chapter 2 – Hardware Information...

  • Page 34: Usb2.0 Wafer Box (5P Pitch: 1.25Mm) (Cn 45,71,72)

    2.4.8 USB2.0 Wafer BOX (5P Pitch: 1.25mm) (CN 45,71,72) Signal Level Signal Signal Type USBD- DIFF USBD+ DIFF 2.4.9 COM5 + COM6 Connector RS232/RS422/RS485 (CN49) Signal Level Signal Signal Type Top Port (COM5) DCD5 ±9V DTR5 ±9V DSR5 RTS5 ±9V Chapter 2 –...

  • Page 35: Com1 + Com2 Connector Rs232/Rs422/Rs485 (Cn60)

    Signal Level Signal Signal Type Top Port (COM5) CTS5 Bottom Port (COM6) DCD6 ±9V DTR6 ±9V DSR6 RTS6 ±9V CTS6 2.4.10 COM1 + COM2 Connector RS232/RS422/RS485 (CN60) Signal Level Signal Signal Type Top Port (COM 1) DCD1 ±9V DTR1 ±9V Chapter 2 –...
  • Page 36 Signal Level Signal Signal Type Top Port (COM 1) DSR1 RTS1 ±9V CTS1 Bottom Port (COM2) DCD2 ±9V DTR2 ±9V DSR2 RTS2 ±9V CTS2 Chapter 2 – Hardware Information...

  • Page 37: Com3 + Com4 Connector Rs232/Rs422/Rs485 (Cn62)

    2.4.11 COM3 + COM4 Connector RS232/RS422/RS485 (CN62) Signal Level Signal Signal Type Top Port (COM3) DCD3 ±9V DTR3 ±9V DSR3 RTS3 ±9V CTS3 Bottom Port (COM4) DCD4 ±9V DTR4 ±9V DSR4 RTS4 ±9V CTS4 Chapter 2 – Hardware Information...

  • Page 38: Lan (Rj-45) + Dual Usb3.2 Gen 1 (Cn73)

    2.4.12 LAN (RJ-45) + Dual USB3.2 Gen 1 (CN73) Signal Level Signal Signal Type MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+ DIFF MDI2- DIFF MDI1- DIFF MDI3+ DIFF MDI3- DIFF Signal Level Signal Signal Type +5VSB USB3_D- DIFF USB3_D+ DIFF USB3_SSRX−...

  • Page 39: Lan (Rj-45) + Dual Usb3.2 Gen 1 (Cn74)

    Signal Signal Type Signal Level USB3_SSTX− DIFF USB3_SSTX+ DIFF +5VSB USB4_D- DIFF USB4_D+ DIFF USB4_SSRX− DIFF USB4_SSRX+ DIFF USB4_SSTX− DIFF USB4_SSTX+ DIFF 2.4.13 LAN (RJ-45) + Dual USB3.2 Gen 1 (CN74) Signal Signal Type Signal Level MDI0+ DIFF MDI0- DIFF MDI1+ DIFF MDI2+...
  • Page 40 Signal Signal Type Signal Level MDI3+ DIFF MDI3- DIFF Signal Level Signal Signal Type +5VSB USB1_D- DIFF USB1_D+ DIFF USB1_SSRX− DIFF USB1_SSRX+ DIFF USB1_SSTX− DIFF USB1_SSTX+ DIFF +5VSB USB2_D- DIFF USB2_D+ DIFF USB2_SSRX− DIFF USB2_SSRX+ DIFF USB2_SSTX− DIFF USB2_SSTX+ DIFF Chapter 2 –...

  • Page 41: Hdmi Port (Cn75)

    2.4.14 HDMI Port (CN75) Signal Level Signal Signal Type HDMI1_DATA2_P HDMI1_DATA2_N DIFF HDMI1_DATA1_P DIFF HDMI1_DATA1_N DIFF HDMI1_DATA0_P DIFF HDMI1_DATA0_N DIFF HDMI1_CLK_P DIFF HDMI1_CLK_N DIFF HDMI1_SCL DIFF HDMI1_SDA DIFF +V5S_HDMI_CON1 HDMI1_HPD Chapter 2 – Hardware Information...

  • Page 42: Hdmi Port (Cn76)

    2.4.15 HDMI Port (CN76) Signal Signal Type Signal Level HDMI2_DATA2_P DIFF HDMI2_DATA2_N DIFF HDMI2_DATA1_P DIFF HDMI2_DATA1_N DIFF HDMI2_DATA0_P DIFF HDMI2_DATA0_N DIFF HDMI2_CLK_P DIFF HDMI2_CLK_N DIFF HDMI2_SCL DIFF HDMI2_SDA DIFF +V5S_HDMI_CON2 HDMI2_HPD Chapter 2 – Hardware Information...

  • Page 43: Lpc Port (Lpc1)

    2.4.16 LPC Port (LPC1) Signal Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V +3.3V +3.3V LFRAME# LRESET# +3.3V LCLK LDRQ0 LDRQ1 SERIRQ +3.3V Chapter 2 – Hardware Information...

  • Page 44: Mini Card Slot (Full-Sized) (Pcie1)

    2.4.17 Mini Card Slot (Full-Sized) (PCIE1) Signal Signal Type Signal Level PCIE_WAKE# +3.3V +3.3V +1.5V +1.5V PCIE_CLK_REQ# PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF Chapter 2 – Hardware Information...
  • Page 45 Signal Signal Type Signal Level W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 46: Mini Card Slot With Msata (Full Sized) (Pcie2)

    Signal Signal Type Signal Level +1.5V +1.5V +3.3VSB +3.3V 2.4.18 Mini Card Slot with mSATA (Full Sized) (PCIE2) Signal Signal Type Signal Level PCIE_WAKE# +3.3V +3.3V +1.5V +1.5V PCIE_CLK_REQ# Chapter 2 – Hardware Information...
  • Page 47 Signal Signal Type Signal Level PCIE_REF_CLK- DIFF PCIE_REF_CLK+ DIFF W_DISABLE# +3.3V PCIE_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF Chapter 2 – Hardware Information...
  • Page 48 Signal Signal Type Signal Level USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 49: Sata Pwr (Pwr 1,2)

    2.4.19 SATA PWR (PWR 1,2) Signal Level Signal Signal Type +12V +12V 2.4.20 SATA Port (SATA 3,4) Signal Level Signal Signal Type SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF Chapter 2 – Hardware Information...

  • Page 50: Sim Slot (Sim1)

    2.4.21 SIM Slot (SIM1) Signal Signal Type Signal Level UIM_PWR UIM_RST UIM_CLK UIM_VPP UIM_DATA Chapter 2 – Hardware Information...

  • Page 51: Cpu Installation

    CPU Installation Before installing the CPU, ensure the system is powered down and disconnect the power cord from the system. Make sure you have the processor ready to install. See Chapter 1 Specifications for list of compatible CPU/processors. Step 1: Remove the screws on the front and back of the BOXER-6839-CFL as shown in the figure below (six in total), and remove the top heatsink.
  • Page 52 Step 2: Install the CPU into the socket and place the thermal pad on top of the processor. Step 3: Place the heatsink back on and secure with the screws you removed in Step 1. Chapter 2 – Hardware Information...

  • Page 53: Expansion Card Installation

    Expansion Card Installation Before installing expansion cards, ensure the system is powered down and disconnect the power cord from the system. Make sure you have the expansion card ready to install. See Chapter 1 for expansion card requirements and specifications. Step 1: Remove the eight (8) screws from the bottom of the BOXER-6839-CFL.
  • Page 54 Step 2: Remove the expansion bay cover and install the expansion card. Secure to the chassis with a screw. Step 3: Reattach the expansion card bracket and secure with the two screws removed in Step 1. Then, replace and secure the bottom panel with the eight screws removed in Step 1.

  • Page 55: 2.5" Sata Drive Installation

    2.5” SATA Drive Installation Before installing the 2.5” SATA drive(s), ensure the system is powered down and disconnect the power cord from the system. Make sure you have the 2.5” SATA drive(s) ready to install. See Chapter 1 for 2.5” SATA drive requirements and specifications. Step 1: Remove the eight (8) screws from the bottom of the BOXER-6839-CFL.
  • Page 56 Step 2: Install the 2.5” SATA drives into the SATA drive mount shown. Secure with four side screws. Step 3: Attach the SATA and SATA Power cables to the board and the SATA drive. Step 4: Replace the bottom panel and secure with the eight (8) screws you removed in Step 1.

  • Page 57: Wallmount Assembly

    Wallmount Assembly Step 1: Line up the wallmount brackets in the mounting kit with the holes as shown. The middle hole should line up with the bottom panel screw such that you can easily remove the screw from the bottom panel without having to remove the bracket Step 2: Use the four screws included with the wallmount kit to secure the wall mount brackets.

  • Page 58: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 59: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 60: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 61: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 62: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 63: Advanced: Trusted Computing

    3.4.1 Advanced: Trusted Computing Options Summary Security Device Enable Optimal Default, Failsafe Default Support Disable Enable or Disable BIOS support for security device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SHA-1 PCR Bank SHA256 PCR Bank...
  • Page 64 Options Summary Platform Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Platform Hierarchy Storage Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Storage Hierarchy Endorsement Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Endorsement Hierarchy TPM2.0 UEFI Spec TCG_2 Optimal Default, Failsafe Default...

  • Page 65: Advanced: Cpu Configuration

    3.4.2 Advanced: CPU Configuration Options Summary Intel (VMX) Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology. Active Processor Cores Optimal Default, Failsafe Default Number of cores to enable in each processor package. Intel(R) SpeedStep(tm) Disabled Enabled...
  • Page 66 Options Summary Turbo Mode Disabled Enabled Optimal Default, Failsafe Default Enable/Disable Processor Turbo Mode (requires Intel Speed Step or Intel Speed Shift to be available or enabled). C states Disabled Optimal Default, Failsafe Default Enabled Enable/Disable CPU Power Management. Allows CPU to go C states when it’s not 100% utilized Hyper-Threading Disabled...

  • Page 67: Advanced: Pch-Fw Configuration

    3.4.3 Advanced: PCH-FW Configuration Options Summary ME State Enabled Optimal Default, Failsafe Default Disabled When Disabled ME will be put into ME Temporarily Disabled Mode. AMT BIOS Feature Enabled Optimal Default, Failsafe Default Disabled When disabled AMT BIOS Features are no longer supported and user is no longer able to access MEBx Setup.

  • Page 68: Firmware Update Configuration

    3.4.3.1 Firmware Update Configuration Options Summary ME FW Image Re-Flash Enabled Disabled Optimal Default, Failsafe Default Enable/Disable ME FW Image Re-Flash function. Chapter 3 – AMI BIOS Setup...

  • Page 69: Ptt Configuration

    3.4.3.2 PTT Configuration Options Summary ME FW Image Re-Flash dTPM Optimal Default, Failsafe Default Selects TPM device: PTT or dTPM. PTT – Enables PTT in SkuMgr dTPM 1.2 – Disables PTT in SkuMgr Warning! PTT/dTPM will be disabled and all saved data will be lost. Chapter 3 –...

  • Page 70: Advanced: Sata Configuration

    3.4.4 Advanced: SATA Configuration Options Summary SATA Mode AHCI Mode Optimal Default, Failsafe Default Selection Intel RST Premium With Intel Optane System Acceleration Determines how SATA controller(s) operate. Aggressive LPM Enabled Support Disabled Optimal Default, Failsafe Default Enable PCH to aggressively enter link power state. mSATA Enabled Optimal Default, Failsafe Default...

  • Page 71: Advanced: Usb Configuration

    3.4.5 Advanced: USB Configuration Options Summary XHCI Hand-off Enabled Optimal Default, Failsafe Default Disabled This is a workaround for OSes without XHCI Hand-off support. The XHCI ownership change should be claimed by XHCI driver. USB Mass Storage Driver Enabled Optimal Default, Failsafe Default Support Disabled Enable/Disable USB Mass Storage Driver Support.

  • Page 72: Advanced: Hardware Monitor

    3.4.6 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 73: Advanced: Sio Configuration

    3.4.7 Advanced: SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 74: Serial Port 1 Configuration

    3.4.7.1 Serial Port 1 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default settings IO=3F8h; IRQ = 4; IO=2F8h; IRQ = 3; Allows the user to change the device resource settings.

  • Page 75: Serial Port 2 Configuration

    3.4.7.2 Serial Port 2 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default settings IO=2F8h; IRQ = 3; IO=3F8h; IRQ = 4; Allows the user to change the device resource settings.

  • Page 76: Serial Port 3 Configuration

    3.4.7.3 Serial Port 3 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default settings IO=3E8h; IRQ = 11; IO=2E8h; IRQ = 11; Allows the user to change the device resource settings.

  • Page 77: Serial Port 4 Configuration

    3.4.7.4 Serial Port 4 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default settings IO=2E8h; IRQ = 11; IO=3E8h; IRQ = 11; Allows the user to change the device resource settings.

  • Page 78: Serial Port 5 Configuration

    3.4.7.5 Serial Port 5 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default settings IO=2D0h; IRQ = 11; IO=2C0h; IRQ = 11; Allows the user to change the device resource settings.

  • Page 79: Serial Port 6 Configuration

    3.4.7.6 Serial Port 6 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enabled or Disabled this Logical Device. Device resource USB Automatic Setting Optimal Default, Failsafe Default settings IO=2C0h; IRQ = 11; IO=2D0h; IRQ = 11; Allows the user to change the device resource settings.

  • Page 80: Advanced: Network Stack Configuration

    3.4.8 Advanced: Network Stack Configuration Network Stack Disabled: Options Summary Network Stack Disabled Enabled Optimal Default, Failsafe Default Enable/Disable UEFI Network Stack Chapter 3 – AMI BIOS Setup...
  • Page 81 Network Stack Enabled: Options Summary Network Stack Disabled Enabled Optimal Default, Failsafe Default Enable/Disable UEFI Network Stack Ipv4 PXE Support Disabled Enabled Optimal Default, Failsafe Default Enable/Disable IPv4 PXE boot support. If disabled, IPv4 PXE boot support will not be available. Ipv4 HTTP Support Disabled Optimal Default, Failsafe Default...
  • Page 82 Options Summary Media detect count Optimal Default, Failsafe Default Number of times the presence of media will be checked. Use either +/- or numeric keys to set the value. Chapter 3 – AMI BIOS Setup...

  • Page 83: Advanced: Digital Io Port Configuration

    3.4.9 Advanced: Digital IO Port Configuration Options Summary DIO Type Output Optimal Default, Failsafe Default Input Set DIO as Input or Output DIO Data High Optimal Default, Failsafe Default Set is output level when DIO pin is output Chapter 3 – AMI BIOS Setup...

  • Page 84: Advanced: Power Management

    3.4.10 Advanced: Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. AC Power Loss Last State Optimal Default, Failsafe Default Power On Power Off Select power state when power is re-applied after a power failure. RTC wake system Disabled Optimal Default, Failsafe Default...
  • Page 85 Options Summary Wake up hour Select 0-23; For example enter 3 for 3am and 15 for 3pm Wake up minute 0 – 59 Wake up second 0 - 59 Chapter 3 – AMI BIOS Setup...

  • Page 86: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 87: Chipset: System Agent (Sa) Configuration

    3.5.1 Chipset: System Agent (SA) Configuration Options Summary SA GV Enabled Optimal Default, Failsafe Default Disabled Fixed Low Fixed High System Agent Geyserville. Fixed Low/Mid/High: SA GV disabled, MRC only runs tasks from Low, Mid, or High point. SA GV will be disabled on DT/Halo CPUs, regardless of this setting. PM Support Enabled Optimal Default, Failsafe Default...
  • Page 88 Options Summary DVMT Total Gfx Mem 128M 256M Optimal Default, Failsafe Default Select DVMT5.0 Total Graphic Memory sized used by the Internal Graphics Device. VT-d Enabled Disabled Optimal Default, Failsafe Default VT-d capability. Skip Scaning of Enabled External Gfx Card Disabled Optimal Default, Failsafe Default If Enabled, it will not scan for External Gfx Card on PEG and PCH PCIE Ports...

  • Page 89: Chipset: Pch-Io Configuration

    3.5.2 Chipset: PCH-IO Configuration Options Summary HD Audio Enabled Optimal Default, Failsafe Default Disabled Control the Detection of the Audio device. Disabled = HDA will be unconditionally disabled. Enabled = HDA will be unconditionally enabled. PCI Express x4 Slot(x1) Auto Optimal Default, Failsafe Default Speed (C246 Only) Gen 1...
  • Page 90 Options Summary Mini-Card 1 Slot PCIe Auto Optimal Default, Failsafe Default Speed Gen 1 Gen 2 Configure PCIe Speed. Mini-Card 2(PCIE2) mSATA Optimal Default, Failsafe Default mSATA/PCIe Selection PCIe Select mSATA or PCIe function for Mini-Card 2(PCIE2). Mini-Card 2 Slot PCIe Auto Optimal Default, Failsafe Default Speed...

  • Page 91: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 92: Security: Secure Boot

    3.6.1 Security: Secure Boot Options Summary Secure Boot Disable Optimal Default, Failsafe Default Enable Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System mode is in User mode. The mode change requires platform reset. Secure Boot Mode Standard Custom...
  • Page 93 Options Summary Key Management Enables expert users to modify Secure Boot Policy variables without full authentication Chapter 3 – AMI BIOS Setup...

  • Page 94: Key Management

    3.6.1.1 Key Management Options Summary Factory key Provision Disabled Optimal Default, Failsafe Default Enabled Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode. Restore Factory Keys Press ‘Yes’ to install factory default keys Force System to User Mode.
  • Page 95 Options Summary Enroll Efi Image Allow the image to run in Secure Boot mode. Enroll SHA256 Hash Certificate of a PE Image into Authorized Signature Database (db). Device Guard Ready Remove ‘UEFI CA’ from Press ‘Yes’ to remove ‘UEFI CA’ from SB Device Guard ready system must not list ’Microsoft UEFI CA’...
  • Page 96 Secure Boot variable |Size | Keys#| key Source Authorized Details Enroll Factory Defaults or load certificates from a Signatures| 4296 | 3 file: | No Key 1.Public key Certificate: Export a)EFI_SIGNATURE_LIST b)EFI_CERT_X509 (DER) Update c)EFI_CERT_RSA2048 (bin) d)EFI_CERT_SHAXXX Append 2.Authenticated UEFI Variable 3.EFI PE/COFF Image(SHA256) Delete Key Source:...
  • Page 97 Secure Boot variable |Size | Keys#| key Source OsRecovery Update Enroll Factory Defaults or load certificates from a Signatures| 0 | 0 | No file: 1.Public key Certificate: a)EFI_SIGNATURE_LIST b)EFI_CERT_X509 (DER) c)EFI_CERT_RSA2048 (bin) Append d)EFI_CERT_SHAXXX 2.Authenticated UEFI Variable 3.EFI PE/COFF Image(SHA256) Key Source: Factory, External, Mixed Chapter 3 –...

  • Page 98: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enables or disables Quiet Boot option. Chapter 3 – AMI BIOS Setup...

  • Page 99: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 100: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 101: Drivers Download And Installation

    Drivers Download and Installation Drivers for the BOXER-6839-CFL can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/fanless-embedded-box-pc-socket-type-boxer-6839-CFL Download the driver(s) you need and follow the steps below to install them. Install Chipset Drivers Open the Step1 - Chipset folder and select your OS Run the SetupChipset.exe file in the folder Follow the instructions...
  • Page 102 Install LAN Drivers Open the Step4 - LAN folder and select your OS Run the PROWinx64_23.5.2.exe file in the folder Follow the instructions Drivers will be installed automatically Install Audio Drivers Open the Step5 – Audio folder and select your OS Run the 0008-64bit_Win7_Win8_Win81_Win10_R281.exe file in the folder Follow the instructions Drivers will be installed automatically...

  • Page 103: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 104: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1: Super IO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2: Watchdog relative register table Register BitNum Value...
  • Page 105 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 106 ************************************************************************************ Main VOID // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 107 ************************************************************************************ // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 1 // Procedure : AaeonWDTConfig AaeonWDTConfig () VOID // Disable WDT counting WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 0 // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting();...
  • Page 108 ************************************************************************************ SIOEnterMBPnPMode() VOID IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); SIOExitMBPnPMode() VOID IOWriteByte(SIOIndex, 0xAA); SIOSelectLDN(byte LDN) VOID IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value) VOID Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 <<...

  • Page 109: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 110: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 111 Appendix B – I/O Information...

  • Page 112: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 113 Appendix B – I/O Information...
  • Page 114 Appendix B – I/O Information...
  • Page 115 Appendix B – I/O Information...
  • Page 116 Appendix B – I/O Information...
  • Page 117 Appendix B – I/O Information...
  • Page 118 Appendix B – I/O Information...
  • Page 119 Appendix B – I/O Information...
  • Page 120 Appendix B – I/O Information...
  • Page 121 Appendix B – I/O Information...
  • Page 122 Appendix B – I/O Information...
  • Page 123 Appendix B – I/O Information...

  • Page 124: Memory Address Map

    Memory Address Map Appendix B – I/O Information...

  • Page 125: Appendix C - Digital I/O Ports

    Appendix C Appendix C - Digital I/O Ports...

  • Page 126: Electrical Specifications For Digital I/O Ports

    Electrical Specifications for Digital I/O Ports GPIO70 DIO_0 GPIO71 DIO_1 GPIO72 DIO_2 GPIO73 DIO_3 GPIO74 DIO_4 GPIO75 DIO_5 GPIO76 DIO_6 GPIO77 DIO_7 Appendix C – Digital I/O Information...

  • Page 127: Dio Programming

    DIO Programming BOXER-6839-CFL utilizes FINTEK F81966 chipset as its Digital I/O controller. The following sections detail the procedures to complete its configuration. The AAEON initial DIO program is also attached to help with developing a customized program for your application. There are three steps to complete the configuration setup: Step 1 Enter MB PnP Mode.

  • Page 128: Digital I/O Register

    Digital I/O Register Table 1: SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2: Digital Input relative register table Register BitNum Value...

  • Page 129: C.4 Digital I/O Sample Program

    C.4 Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 130 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 131 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 132 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Information...
  • Page 133 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 134 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

  • Page 135: Appendix D - Glue Removal Procedure

    Appendix D Appendix D – Glue Removal Procedure...

  • Page 136: Removing Glue From Your System

    Removing Glue from Your System To protect components from damage and ensure proper operation out of the box, glue may have been applied to some cables or connectors to keep them in place during shipping. This glue must be removed before attempting to swap components or perform maintenance.
  • Page 137 Step 1: Using an eyedropper or bottle as shown above, apply a few drops of alcohol to the glue. Step 2: Allow the alcohol to soak for 10 seconds, then use a cotton swab or cotton with anti-static tweezers to evenly rub the alcohol over the glue. Step 3: Let soak for 10 more seconds, then use anti-static tweezers to remove the glue.
  • Page 138 If you encounter any issues or need support, please contact your AAEON representative or visit our Support Page at AAEON.com Appendix C – Digital I/O Information...

Table of Contents