Wake-Up Timer Interrupt Function; Related Registers For Function Of Wake-Up Timer Interrupt Function - Epson RX8111CE Applications Manual

RX8111CE

14.2. Wake-up Timer Interrupt Function

The wake-up timer interrupt function generates an interrupt event periodically at any fixed cycle set between 244.14 s and 31.9
years. This function can stop at one time and is available as an accumulative timer.
After the interrupt occurs, the /INT status is automatically cleared .

14.2.1. Related registers for function of wake-up timer interrupt function

Address
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
2Dh
Before entering operation settings, we recommend first clearing the TE bit to "0" .
When the fixed-cycle timer function is not being used, the fixed-cycle Timer Counter0,1 register can be used as a RAM register. In
such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.
1) Down counter for wake-up interrupt timer Timer Counter 2, 1, 0
This register is used to set the default (preset) value for the counter. Any count value from 1 (000001h) to 16777216 (FFFFFFh) can
be set.
Be sure to write "0" to the TE bit before writing the preset value.
When TE = 0, read out data of timer counter is default (Preset) value. And when TE = 1, read out data of timer counter is just
counting value. But, when access to timer counter data, counting value is not held.
Therefore, for example, perform twice read access to obtain right data, and a way to adopt the case that two data accorded is
necessary.
2) TSEL1, TESL0 bit
This combination decides the source clock of count down period.
The source clock selection should be done after TE bit setting to "0".
TSEL1
(bit 1)
0
0
1
1
The /INT pin's auto reset time (tRTN) varies as shown above according to the source clock setting.
The first countdown shortens than a source clock.
The example of the error of the first countdown: A value to preset is 0004h
TE
Inner source clock
Down counter
TF
Table 16 Wake-up interrupt timer register
Function bit 7
Timer Counter 0 128
Timer Counter 1 32768
8388608 4194304 2097152 1048576
Timer Counter 2
Extension Register FSEL1 FSEL0
Flag Register POR
Control Register
Timer Control
Table 17 TSEL bit, selection of source clock
TSEL0
(bit 0)
0
1
0
1
Cycle error
4
Figure 18 Wake-up timer initial sequence (cycle error)
bit 6 bit 5
64 32
16384 8192
USEL
z UF
z z UIE
z z z
Source clock
Once per 244.14 s
4096 Hz
64 Hz Once per 15.625 ms
1 Hz
1/60 Hz
Designed cycle
正しい周期
3
Page − 24
bit 4 bit 3 bit 2
16 8 4
4096 2048 1024
524288 262144 131072 65536
TE WADA ETS
TF AF EVF
TIE AIE EIE
z
TBKON TBKE
Once per 1 second
Once per minute
2 1
bit 1 bit 0
2 1
512 256
TSEL1 TSEL0
VLF XST
z STOP
TMPIN TSTP
Auto reset time
(tRTN)
122 s
7.813 ms
7.813 ms
7.813 ms
4
TF bit "0"⇒ "1"
ETM61E-01