Xycom XVME 200 Manual page 36

XVME-200/290 Manual
December, 1987
Table 3-3 shows how pins
data transceivers. Remember, each PI/T chip has its own PORT A and B, and thus
there is a total of 4 lines which are used to control the direction of the four data
transceivers (refer to the Module Block Diagram, Figure l-l).
Table 3-3. PORT A and B Data Transceiver Direction Control *
\
PC0
output
0
1
* These directions are the same for both PI/T chips.
PI/T
assume the same direction, this direction must be
consistent with PC0 as shown in Table 3-3. PI/T
pins PBO-PB7 must all be programmed to assume the
same direction, this direction must be consistent with
PC1 as shown in Table 3-3. Failure to observe these
conventions will cause signal contention.
Port A and B Reset State
3.4.1
During a VMEbus reset, PI/T PORTS A, B, and C all assume an input direction.
Therefore, I/O signals PAO-PA7 and PBO-PB7 all assume an input direction during a
reset. This means that if the I/O signals are being used in an application as
outputs, they will have a "high" reset state.
to be used on lines which must be negated on power-up or system reset.
receivers of these active "low" outputs should limit their
guarantee that they will be negated upon reset.
PC0
and PC1 affect the direction of the PORT A and B
PC1 output Data Line Transceiver Direction I
0
1
CAUTION
pins PA0-PA7 must all be programmed to
PA0-PA7 are OUTPUTS
PA0-PA7 are INPUTS
PB0-PB7 are OUTPUTS
PB0-PB7 are INPUTS
Thus, active "low" outputs would have
3-9
The
value below 250uA to