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AVR1306: Using the XMEGA Timer/Counter
Features
• True 16 bit operation
• Double buffered timer period setting
• 4 (2) compare or capture channels per timer
- 4 channels on each Timer 0
- 2 channels on each Timer 1
- Double buffered
• 32 bit operation with 32 bit input capture by timer cascading
• Event counter
• Timer overflow and error interrupts (and events)
• Input capture interrupts (and events)
1 Introduction
The XMEGA™ Timer/Counter modules are true 16-bit Timer/Counters with Input
Capture and Pulse Width Modulation (PWM) functionality.
This application note gives an introduction on how to use the XMEGA
Timer/Counter modules for timing, Input Capture and PWM.
8-bit
Microcontrollers
Application Note
Rev. 8045A-AVR-02/08
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Table of Contents
Related Manuals for Atmel AVR1306
Summary of Contents for Atmel AVR1306
- Page 1 AVR1306: Using the XMEGA Timer/Counter Features • True 16 bit operation • Double buffered timer period setting 8-bit • 4 (2) compare or capture channels per timer - 4 channels on each Timer 0 Microcontrollers - 2 channels on each Timer 1 - Double buffered •...
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Page 2: Module Overview
Figure 3-1 shows how the output compare channels are connected to the associated I/O port. Timer0 has its outputs connected to pins 0- 3 within the port, while Timer1 is mapped to pins 4 and 5. AVR1306 8045A-AVR-02/08... -
Page 3: Clock Sources
AVR1306 Figure 3-1. Output compare to I/O port pin mapping PORTx TCx0 TCx1 3.2 Clock Sources The available clock source selections for the XMEGA TC modules are listed in Table 3-1. Table 3-1. XMEGA Timer/Counter clock sources. Symbol Clock selection... -
Page 4: Period Setting
Note that when a set of event channels have been selected for the TC, this does not mean that these event channels are used exclusively by the TC. The TC simply “listens” to the selected channels and is able to receive events on these event channels. AVR1306 8045A-AVR-02/08... -
Page 5: Modes Of Operation
AVR1306 Table 3-2. Event channel to input capture channel mapping. Input capture channel Global event channel (N + 1) % 8 C (If available) (N + 2) % 8 D (If available) (N + 3) % 8 Example 1: EVSEL3 = 1 and EVSEL[2:0] = 0 means that input capture channels A, B, C and D are triggered by event channels 0, 1, 2 and 3 respectively. - Page 6 For FRQ the period (T) is controlled by the CCA[H:L] register instead of PER[H:L], which in this case is not in use. In addition the Waveform Generation (WG) output is toggled on each compare match between CNT[H:L] and CCA[H:L] as shown in Figure 3-3. AVR1306 8045A-AVR-02/08...
- Page 7 AVR1306 Figure 3-3. Frequency Generation Mode Period (T) Direction Change CNT written "update" TCNT WG Output The waveform generated will have a maximum frequency of f /2 when CCA[H:L] is set to zero (0x0000). The waveform frequency is defined by Equation 3-1.
- Page 8 PWM mode. The period register (PER[H:L]) defines the PWM resolution. The minimum resolution allowed for this module is 2-bit (PER[H:L]=0x0003), and maximum resolution is 16-bit (PER[H:L]=0xFFFF). Equation 3-4 can be used for calculate the exact resolution for dual-slope PWM. AVR1306 8045A-AVR-02/08...
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Page 9: Timer/Counter Commands
AVR1306 Equation 3-4. PWM Resolution, Dual Slope PWM Mode The PWM base frequency depends on the period setting (PER[H:L]), system clock frequency and clock prescaler and can be calculated using Equation 3-5. Equation 3-5. Frequency calculation, Dual Slope PWM Mode ⋅... - Page 10 2. Write CNTH. This will cause CNTL to be updated with the contents of the TEMP register at the same time as CNTH is updated. The result is that the 16-bit CNT[H:L] value is updated in the same clock cycle. AVR1306 8045A-AVR-02/08...
- Page 11 AVR1306 Figure 4-2. 16-bit write access. CNTH CNTL TEMP R(n+1) CNTH CNTL TEMP R(n+1) 4.3 Implications of Having a Shared TEMP Register Since one TEMP register is shared for all 16-bit registers within one TC module, there is a possibility of register corruption if the necessary measures are not taken.
- Page 12 32-bit value is to stop the TC, write the value and start the TC again. 5.3 Using 32-bit Input Capture A 32-bit Timer/Counter can be set up to perform 32-bit input capture. First, a 32-bit Timer/Counter must be set up as described in section 5.1. Both TCs are configured AVR1306 8045A-AVR-02/08...
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Page 13: Getting Started
AVR1306 for input capture, with the same event channels as capture sources. However, there is a one clock-cycle delay in the propagation of the overflow bit from the low word TC to the high word TC. This means that it is necessary to delay the event to the high word TC to ensure the correct input capture value. -
Page 14: Event Counting
In this configuration, the CNT[H:L] register will contain the number of times a switch connected to PC0 has been pressed. After 5 presses, an overflow interrupt service handler will be triggered, toggling PC1 while CNT[H:L] wraps around to 0. AVR1306 8045A-AVR-02/08... -
Page 15: Advanced Features
AVR1306 6.6 Setting up a 32-bit Timer/Counter With Input Capture Task: Configure TCC0 and TCC1 as one 32-bit TC with input capture channel A triggered by a falling edge on PC0. Event channel 0 is used for overflow propagation, while the input capture signal from PC0 is routed through event channel 1. -
Page 16: Driver Implementation
For more details about Doxygen please visit http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with the source code accompanying this application note, available from the readme.html file in the source code folder. AVR1306 8045A-AVR-02/08... - Page 17 BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein.