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will read the enabled time value from the option and set the OS Watchdog timer for that value (5, 10, 15, or 20
minutes) before trying to load the operating system. If the OS Watchdog Timer is enabled, the timer is
repurposed as an OS Watchdog timer and is referred to by that title as well. WARNING: The BIOS may
incorrectly determine that a removable media is a hard drive if the media emulates a hard drive. In this case,
the OS Watchdog timer will not be automatically disabled.
If the BIOS is going to boot to a known PXE-compliant device, then the BIOS reads a user option for OS
Watchdog Timer for PXE Boots and either disables the timer or enables the timer with a value read from the
option (5, 10, 15, or 20 minutes). If the OS Watchdog Timer is enabled, the timer is repurposed as an OS
Watchdog Timer and is referred to by that title as well.
If the OS Watchdog Timer is enabled and if a boot password is enabled, the BIOS will disable the OS
Watchdog Timer before prompting the user for a boot password regardless of the OS Watchdog Timer option
setting. Also, if the user has chosen to enter BIOS setup, the timer will be disabled regardless of option
settings. The mBMC retains status bits that can be read by the BIOS later in the POST for the purpose of
logging the appropriate event into the SEL, and displaying an appropriate error message to the user. As the
timer may be repurposed, the BIOS and BMC will also keep track of which timer expired (early FRB2, late
FRB2, or OS Watchdog) and display the appropriate error message to the user.
All of the user options are intended to allow a system administrator to set up a system such that during a
normal boot no gap exists during POST that is not covered by the watchdog timer. Options are provided by
the BIOS to control the policy applied to OS Watchdog timer failures. By default, an OS Watchdog Timer
failure will not cause any action. Other options provided by the BIOS are for the system to reset or power off
watchdog timer failure.
Treatment of Failed Processors
All the failures (FRB3, FRB2, and FRB1), including the failing processor, are recorded into the system event
log (SEL). The FRB-3 failure is recorded automatically by the mBMC while the FRB2, and FRB1 failures are
logged to the SEL by the BIOS. In the case of an FRB2 failure, some systems will log additional information
into the OEM data byte fields of the SEL entry. This additional data indicates the last POST task that was
executed before the FRB2 timer expired. This information may be useful for failure analysis.
Memory Error Handling
The chipset will detect and correct single-bit errors and will detect all double-bit memory errors. The chipset
supports 4-bit single device data correction (SDDC) when in dual channel mode.
Both single-bit and double-bit memory errors are reported to baseboard management by the BIOS, which
handles SMI events generated by the MCH.
Memory Error Handling can be enabled or disabled in system BIOS Setup.
Memory Error Handling in RAS Mode
The MCH supports two memory RAS modes: Sparing and Mirroring. Enabling of Sparing or Mirroring feature
are mutually-exclusive. Use system BIOS Setup to configure memory RAS mode.
The following table shows memory error handling with the mBMC.
Chapter 4
Table 1. Memory Error Handling mBMC
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