Texas Instruments TRF7960A Manual page 49

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6.14.1.2.3 TX Timer High Byte Control Register (0x04)
Table 6-21 describes the bit fields of the TX Timer High Byte Control register. This register sets timings.
Default Value: 0xC2, set at POR = H or EN = L and at each write to the ISO Control register
BIT NO. BIT NAME
B7 tm_st1
B6 tm_st0
B5 tm_lengthD
B4 tm_lengthC
B3 tm_lengthB
B2 tm_lengthA
B1 tm_length9
B0 tm_length8
6.14.1.2.4 TX Timer Low Byte Control Register (0x05)
Table 6-22 describes the bit fields of the TX Timer Low Byte Control register. This register sets timings.
Default Value: 0x00, set at POR = H or EN = L and at each write to the ISO Control register
BIT NO. BIT NAME
B7 tm_length7
B6 tm_length6
B5 tm_length5
B4 tm_length4
B3 tm_length3
B2 tm_length2
B1 tm_length1
B0 tm_length0
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Table 6-21. TX Timer High Byte Control Register (0x04)
FUNCTION
Timer start condition
Timer start condition
Timer length MSB
Timer length
Timer length
Timer length
Timer length
Timer length LSB
Table 6-22. TX Timer Low Byte Control Register (0x05)
FUNCTION
Timer length MSB
Timer length
Timer length
Timer length
Timer length
Timer length
Timer length
Timer length LSB
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SLOS732G – JUNE 2011 – REVISED MARCH 2020
DESCRIPTION
tm_st1 = 0, tm_st0 = 0: beginning of TX SOF
tm_st1 = 0, tm_st0 = 1: end of TX SOF
tm_st1 = 1, tm_st0 = 0: beginning of RX SOF
tm_st1 = 1, tm_st0 = 1: end of RX SOF
See Table 6-22 for timer length description.
DESCRIPTION
Defines the time when delayed transmission is started.
RX wait range is 590 ns to 9.76 ms (1 to 16383),
Step size is 590 ns,
All bits low = timer disabled (0x00)
Preset to 0x00 for all other protocols.
TRF7960A
TRF7960A
Detailed Description 49