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There are two ways to start the transmit operation:
•
Send the transmit command and the number of bytes to be transmitted first, and then start to send the
data to the FIFO. The transmission starts when first data byte is written into the FIFO.
•
Load the number of bytes to be sent into registers 0x1D and 0x1E and load the data to be sent into the
FIFO (address 0x1F), followed by sending a transmit command (see Direct Commands section). The
transmission then starts when the transmit command is received.
If the data length is longer than the FIFO, the external system MCU is warned when the
majority of data from the FIFO was already transmitted by sending and interrupt request with
flag in IRQ register to indicate a FIFO low or high status. The external system should
respond by loading next data packet into the FIFO.
At the end of a transmit operation, the external system MCU is notified by interrupt request (IRQ) with a
flag in the IRQ register (0x0C) indicating TX is complete (example value = 0x80).
The TX Length registers also support incomplete byte transmission. The high two nibbles in register 0x1D
and the nibble composed of bits B4 to B7 in register 0x1E store the number of complete bytes to be
transmitted. Bit B0 in register 0x1E is a flag indicating that there are also additional bits to be transmitted
which do not form a complete byte. The number of bits is stored in bits B1 to B3 of the same register
(0x1E).
Some protocols have options so there are two sublevel configuration registers to select the TX protocol
options.
•
ISO14443B TX Options register (0x02). It controls the SOF and EOF selection and EGT selection for
the ISO/IEC 14443 B protocol.
•
ISO14443A High-Bit-Rate and Parity Options register (0x03). This register enables the use of different
bit rates for RX and TX operations in ISO/IEC 14443 high-bit-rate protocol. Besides that, it also selects
the parity method in case of ISO/IEC 14443 A high bit rate.
The digital section also has a timer. The timer can be used to start the transmit operation at a precise time
in accordance with a selected event. This is necessary if the tag expects a replay in exact time window
following the tag response. This is normally not the case with existing protocols but is needed in protocols
when using 'fixed slot' command.
The TX timer uses two registers (register addresses 0x04 and 0x05). Register 0x04 uses 2 bits (B7 and
B6) to define the trigger conditions. The remaining 6 bits of register 0x04 are the upper bits, and the 8 bits
in register address 0x05 are the lower bits that preset the counter. The range of this counter is from 590
ns to 9.7 ms, in 590-ns increments.
6.11 Transmitter – External Power Amplifier or Subcarrier Detector
The TRF7960A can be used in conjunction with an external TX power amplifier or external subcarrier
detector for the receiver path. If this is the case, Bit B6 of the Regulator and I/O Control register (0x0B)
must be set to 1. This setting has two functions: First, to provide a modulated signal for the transmitter, if
needed. Second, to configure the TRF7960A receiver inputs for an external demodulated subcarrier input.
The design of an external power amplifier requires detailed RF knowledge. There are also readily
designed and certified high-power HF reader modules on the market.
6.12 Communication Interface
6.12.1 General Introduction
The communication interface to the reader can be configured in two ways: with a eight line parallel
interface (D0:D7) plus DATA_CLK, or with a 3- or 4-wire Serial Peripheral Interface (SPI). The SPI
interface uses traditional master out/slave in (MOSI), master in/slave out (MISO), IRQ, and DATA_CLK
lines. The SPI can be operated with or without using the slave select line.
Copyright © 2011–2020, Texas Instruments Incorporated
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TRF7960A
SLOS732G – JUNE 2011 – REVISED MARCH 2020
Detailed Description
TRF7960A
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