Frequency Synthesizer - SIGNALCORE SC5506A Operating & Programming Manual

Frequency Synthesizer

The synthesizer section of the SC5506A comprises a multiple phase-locked loop architecture whose base
frequency reference is a 10 MHz TCXO. The user may choose to phase-lock this base reference to an
external source if required. The 100 MHz VCXO is phase-locked to the TCXO for frequency stability. While
the TCXO determines the very close-in phase noise, the VCXO phase noise determines the system phase
noise in the frequency offset range of approximately 1 kHz to 30 kHz. The 100 MHz VCXO provides the
reference signal to the main RF signal synthesizer, which is comprised of three phase-locked loops (PLLs)
and a direct digital synthesis (DDS) oscillator. The "fine" PLL provides a tuning resolution of few millihertz
over a narrow frequency range, while the "coarse" PLL tunes in steps of a few megahertz over several
gigahertz of range. The "main" or summing PLL combines the signals of the "coarse" and "fine" loops into
one broad tuning signal with fine tuning capability.
0-60 dB
DSA
CH1
ALC
MODE
REF
OUT
ENABLE
REF
OUT
REF
IN
REF
DAC
ALC
MODE
0-60 dB
DSA
CH2
Figure 2. Simplified block diagram of the SC5506A dual channel RF signal source.
Using this multiple loop approach produces signals with low phase noise and low phase spurs, high levels
of which exist in single loop architectures such as single fractional-N PLLs. Although a single fractional-N
type PLL may provide fine resolution, its large fractional spurs may make it unusable in certain parts of
the band - especially at frequency regions close the integer boundaries. A multiple loop architecture
allows fine tuning with extremely low phase spurs.
SC5506A Operating & Programming Manual
FILTER
BANK
ALC LOOP

ALC
DAC
LCK
10 MHz
EXT
TCXO
REF
ALC
DAC

ALC LOOP
FILTER
BANK
Rev 2.1.1
VCA 1,2,4,..128 3-6 GHz
N
N
MAIN PLL
COARSE
PLL
100
MHz
VCXO
M
A
COARSE
PLL
MAIN PLL
N
N
3-6 GHz
VCA 1,2,4,..128
FINE PLL
N
DDS
N
N
DDS
N
FINE PLL
9