Warranty ............................4 Copyright & Trademarks ........................ 4 International Materials Declarations ..................... 5 CE European Union EMC Declaration .................... 5 Warnings Regarding Use of SignalCore Products ................5 Physical Description ..........................6 Unpacking ............................6 Nomenclature ..........................6 Setting Up and Configuring the UHFS Device ................6 Front Interface Indicators and Connectors ..................
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SignalCore immediately if the product appears damaged in any way. Nomenclature The name “UHFS” shall be used in this document in reference to both the SC5520A and SC5521A, unless the context requires using SC5520A or SC5521A explicitly. The SC5520A is a PXIe platform module while the SC5521A is a USB/Serial platform module.
20°C above ambient temperature under normal operating conditions. Front Interface Indicators and Connectors The SC5520A is a PXIe-based RF signal source with all RF connectors located on the front face of the module. Its control I/O is via the back PXIe interface connectors.
There are both status and active LED indicator lights for the device, and their functions are listed in Table 1 and Table 2. The active LED indicator lights are user programmable (see register map). Rev 1.1 | SC5520A & SC5521A Hardware Manual...
TFM-115-01-L-D-RA. It also serves as the digital connector interface for RS232/SPI, trigger, and other digital signals. The pin definitions are listed in Table 3. Pinouts are different for different SignalCore products with the same connector type. Please ensure that mating connectors and cables are wired correctly before connection.
All user settings will be lost. System reset capability can also be accessed through the communication header connector. Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Theory and Operation 3 Theory and Operation The UHFS module is an instrument-grade, high performance synthesizer with easy to program register- level control. It functions as a standard synthesized CW source with the added capability of a sweep/list mode that makes it ideal for applications ranging from automated test systems to telecommunication equipment to scientific research labs.
When frequency points are generated based on the start/stop/step set of frequencies, this is (in the context of this product) known as putting the device into sweep. When the sweep function is enabled, Rev 1.1 | SC5520A & SC5521A Hardware Manual...
Theory and Operation the frequency points are incrementally stepped with a constant step size either in a linearly increasing or linearly decreasing fashion. List Function The list function requires that the frequency points are read in from a list provided by the user. The user will need to load the frequency points into the list buffer via the LIST_BUFFER_WRITE register, or have the device read the frequency points into it from the EEPROM.
Hardware Registers 4 Hardware Registers Configuration Registers These are write-only registers to configure the device. The registers vary in length to reduce redundant data and improve the communication speed, especially for SPI and RS232 interfaces. Furthermore, it is vitally important that the length of data written to a register is exact because failure to do so will cause the interfaces to misinterpret the incoming data, leaving the device in a stalled state.
Type Name Width Description 0 = turns off the active LED Mode 1 = turns on the active LED [7:1] Unused Set all bits to zero Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Hardware Registers Register 0x03 SYNTH_MODE (1 Byte) This register configures the PLL loop gain of the local oscillator synthesizers. It also enables or disables faster tuning of the YIG based oscillator of LO1. Type Name Width Description 0 = harmonic offset mode Lock Mode 1 = fracN PLL offset mode 0 = Normal loop gain for better close in phase...
Triangular Waveform 1 = Triangular waveform. Frequency reverses direction at the end of the list and steps back towards the beginning to complete a cycle. Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
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Hardware Registers Bit Type Name Width Description 0 = Software trigger. Software trigger can only be used to start and stop a sweep/list cycle. It does not work for step-on-trigger mode. Soft/Hardware 1 = Hardware trigger. A high-to-low transition on Trigger the TRIGIN pin will trigger the device.
For example, to produce a 10 ms dwell time the value written to this register is 20d. [55:32] Unused Set to zeros. Register 0x0A LIST_CYCLE_COUNT (7 Bytes) This register sets the device to cycle forever. Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Hardware Registers Bit Type Name Width Description 0 = Cycle forever. This will set the device to cycle forever. Any number greater than 0 will set the [31:0] List Cycle Count number of cycles the device will sweep or step through the list then stop.
This register provides a soft trigger to the device. Bit Type Name Width Description Set all bits to zero. Calling this register provides a [7:0] Soft Trigger soft trigger to the device. Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Hardware Registers Register 0x10 RF_FREQUENCY (7 Bytes) This register sets the RF1 frequency. Bit Type Name Width Description RF1 Frequency [55:0] Sets the RF frequency in mHz. Word Register 0x11 RF_LEVEL (3 Bytes) This register sets the RF1 power level. Bit Type Name Width...
0 = Outputs a 10 MHz signal Reference out select 1 = Outputs a 100 MHz signal [7:2] Unused Set all bits to zero. Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Hardware Registers Register 0x18 REFERENCE_DAC_VALUE (3 Bytes) This register allows the user to set or adjust the internal 10 MHz TCXO frequency. Type Name Width Description 14 bit word to set/adjust the internal 10 MHz [13:0] DAC Value TCXO frequency. [23:14] Unused Set all bits to zero.
Hardware Registers Type Name Width Description Data specifies the parameter to retrieve: 0x00 = Current RF Freq (7 valid bytes return) 0x01 = Sweep Start Freq (7 valid bytes return) 0x02 = Sweep Stop Freq (7 valid bytes return) 0x03 = Sweep Step Freq (7 valid bytes return) 0x04 = Sweep Dwell Time (4 valid bytes return) 0x05 = Sweep Cycle Count (4 valid bytes return) [3:0]...
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0 = device temperature normal [19] status 1 = device temperature exceeded recommended 0 = Fix frequency settable via register 0x10 [18] Operate: RF mode 1 = List mode enabled, register 0x10 ignored Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
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Hardware Registers Type Name Width Description Operate: List mode 0 = list mode not triggered [17] running 1 = list mode triggered and running Operate: Ref freq 0 = 10 MHz [16] out select 1 = 100 MHz Operate: External 0 = signal not detected [15] reference detected...
Write to this register to query 8 bytes of data from the calibration EEPROM at the starting address. Bit Type Name Width Description [15:0] Buffer Address The data point (0 – 1023) to read. [22:16] Unused 0 = frequency [23] Select 1 = amplitude Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Hardware Registers Bit Type Name Width Description If frequency: data [63:0] is frequency in mHz. If amplitude: data is amplitude in the following format [63:0] Data [14:0] is absolute amplitude in 100 of dBm [15] is the sign; 0 = pos, 1 = neg [63:16] is invalid Register 0x25 FETCH_DAC_VALUE (1 Byte, 8 Bytes) Write to this register to query 8 bytes of data from the user EEPROM at the starting address.
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Section 2 Communication Interfaces Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Communication Interfaces 5 Communication Interfaces The SC5520A has a PXI express interface, while the SC5521A has 2 communication interfaces: 1. USB and SPI 2. USB and RS232 This section will examine the communication aspects of the product, focusing on data transfer to and from the device on each interface.
= 0.2 ), however, if the external SPI signals do not have clock rate may be as high as 5.0 MHz (T sufficient integrity due to trace issues, the rate should be lowered. Rev 1.1 | SC5520A & SC5521A Hardware Manual SignalCore, Inc.
Communication Interfaces Byte N (MSB) DATA 8 Bit Command/ Reg. Address Byte N-1 (LSB) Figure 4. SPI timing. As mentioned above, the SPI architecture limits the byte rate since after every byte transfer the input and output SPI buffers need to be cleared and loaded respectively by the device SPI engine. Data is transferred between the input buffer and internal register buffers.
The device, upon receiving the first register addressing byte, will wait for all the associated data bytes before acting on the register instruction. Failure to complete the register Rev 1.1 | SC5520A & SC5521A Hardware Manual...
A simple driver using IO controls should be sufficient to read and write byte data to this block of addresses. Although SignalCore provides the driver and API for these products, information is provided here for users who may need to write drivers for a different operating system or a different driver.
8. All 8 bytes must be read to fully clear the transfer buffer. The first byte read is the most significant byte. Rev 1.1 | SC5520A & SC5521A Hardware Manual...
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