Rabbit 4000 User Manual page 27

clock, resulting in no net change due to asymmetry. However, if an odd number of wait
states is used, then the memory access time will be affected slightly
The maximum allowed clock speed must be slightly reduced if the clock is supplied via
the clock doubler. The only signals clocked on the falling edge of the clock are the mem-
ory and I/O write pulses and the early option memory output enable. See Chapter 5 for
more information on the early output enable and write enable options.
The power consumption is proportional to the clock frequency, and for this reason power
can be reduced by slowing the clock when less computing activity is taking place. The
clock doubler provides a convenient method of temporarily speeding up or slowing down
the clock as part of a power management scheme.
Chapter 2 Clocks 17