Dell 6100 Service Manual page 86

A-10 Dell PowerEdge 6100/200 System Service Manual
Table A-6. Advanced Chipset Configuration
Submenu Categories (continued)
Category
MPS Version
Second I/O APIC
PIC Interrupt Routing
IOQ Depth
GAT Mode
Outbound Posting
PCI Line Prefetch
Addr Bit Permuting
Chip Set Register
Settings
Function
Specifies MultiProcessor Specification
(MPS) number used by operating system.
Dell setting is 1.4, the correct value for the
Dell PowerEdge 6100 system. If system
setup program categories are reset, change
this value from 1.1 to 1.4.
Enables or disables (default) the second I/O
Advanced Peripheral Interrupt controller
(APIC) in the MPS tables.
Connects the interrupt mapping to the
microprocessor's local APIC through the
I/O APIC if set to Through IO APIC. If set
to Default (default), the INTR and NMI
signals are connected directly to the micro-
processor's local APIC, bypassing the I/O
APIC.
Configures the In-Order Queue to support a
specified number (8, 1, or Auto Configure
[default]) of pending pipelined transactions
on the microprocessor bus.
Options are Aliased (default) and Normal.
Enables or disables (default) write posting
to the PCI bus from the microprocessor
bus.
Enables (default) or disables up to three
additional cache lines in response to PCI
Line Read and PCI Read Multiple com-
mands.
Enables or disables (default) the memory
controller to swap high-order row selection
bits with low-order bits when computing
the effective memory address.
Configures several performance features of
the computer chipset based on the chipset's
hardware revision level. Set to Auto Con-
figure, which allows the BIOS to optimize
these settings based on your system's
chipset.