Epson RX8111CE Applications Manual page 52

RX8111CE
(2) Multiple time stamp is available with following registers management.
The record area (40h  7Fh) all the time stamp is recorded except 1/1024 sec, WEEK.
1) TSRAM bit
This bit control RAM (40h7Fh) the usage time stamp recording or normal RAM.
TSRAM
Write
2) TSCLR bit (Time Stamp Clear)
The operation of writing "1" to this bit makes address 36h clear to initialize and this bit be reset to "0" automatically.
Time stamp function should be disenabled by resetting ETS to "0" before this operation (Time stamp clear).
TSCLR
Write
3) EISEL bit (Event Interrupt Select)
This bit controls time stamp event interrupt selection.
EISEL
Write
Figure 37 Careful timing process when RTC internal status trigger is used for time stamp
Table 70 TSRAM bit (Time Stamp Clear)
Data Description
40h~7Fh is used a normal (Read/Write enable)
0
Time stamp data is recorded into 20h-28h at event timing.
40h~7Fh is used a time stamp recording memory. (Read/Write enable)
1
User can modify directly RAM data via I
Table 71 TSCLR bit (Time Stamp Clear)
Data Description
Invalid (writing "0" will be ignored)
0
Initializing address 36h register.
TSFUL: 0, TSEMP: 1
1
TSAD2: 1, TSAD1: 1, TSAD0: 1
pointer (1,1,1)
Table 72 EISEL bit (Event Interrupt Select)
Data Description
0 Every time stamp event triggering makes interrupt output.
1 In case of 8 times record (of time stamp) interrupt output occurs.
2
C if necessary.
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