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RX8111CE
(1) Time stamp by self monitor detection of RTC
1) ECMP bit (Enable VCMP)
This bit controls time stamp (VCMP) ON/OFF.
ECMP
Write
2) EVDET bit (Enable VDET)
This bit controls time stamp (VDET) ON/OFF.
When user set EVDET to "1", at least 31.25m sec time interval is needed after INIEN setting to "1". If user cannot set 31.25 ms
interval, unreliable result will be obtained, in such case please ignore the result data. Also, if user used fixed SW combination,
don't use this register. Refer to Figure 38
EVDET
Write
3) EVLOW bit (Enable VLOW )
This bit controls VLOW detection ON/OFF and time stamp (VLOW) ON/OFF. A common register for VLOW function and time
stamp.
EVLOW
Write
4) EXST bit (Enable X'tal Oscillation Stop)
This bit control time stamp (XST) trigger ON/OFF
EXST
Write
Figure 36 Avoiding EVIN pin input event, user read time stamp data.
Table 66 ECMP bit (Enable VCMP)
Data
Description
0
No time stamp event even VCMP is detected.
Time stamp event occurs. When V
1
charging to re-chargeable battery.
Table 67 EVDET bit (Enable VDET)
Data
Description
0
No time stamp event even V
1
When RTC moves to backup mode, time stamp event occurs.
Table 68 EVLOW bit (Enable VLOW)
Data
Description
0
No time stamp event and no VLOW detection.
1
VLOW detection and time stamp event when VLOW is detected.
Table 69 EXST bit (Enable X'tal Oscillation Stop)
Data
Description
0
No time stamp event even when internal crystal oscillation stops.
1
Time stamp event occurs when crystal oscillation stop is detected.
> V
BAT
DD
is detected.
DET1
Page − 47
becomes true, under condition of
ETM61E-01
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