Download
Share
Print this page
  1. Manuals
  2. Brands
  3. FLY Manuals
  4. Cell Phone
  5. SDP100
  6. Technical manual

FLY SDP100 Technical Manual

Hide thumbs Also See for SDP100:

Advertisement

Quick Links

Download this manual
M
ODEL
P
REPARED BY
S
UBJECT
Baseband section
This document provides a description of the baseband section of the SDP100. Most design decisions are explained,
but no detailed calculations are included. Total chip solutions(MT6228, MT6305BN, MT6120) except for RF
Power Amplifier(RF3166) are from MediaTek, Taiwan.
I. MT6228 ( GSM/GPRS Baseband Processor )
1. System OverView
The Revolutionary MT6228 is a leading edge single-Chip solution for GSM/GPRS mobile phones targeting the emerging
applications in digital audio and video. Based on 32bit ARM7EJ-S
performance GPRS Class 12 MODEM, but also provides comprehensive and advanced solutions for handheld multi-
media. But, the SDP100 can only support GPRS Class 8.
The Figure 1 is shown Typical Application for MT6228.
1.1 Platform Feature
SDP100 T
M
ECHNICAL
ANUAL
SDP100
H/W
T
M
ECHNICAL
ANUAL
Figure 1 : Typical Application for MT6228
V
ERSION
D
ATE
P
AGE
TM
RISC processor, MT6228 not only features high
V_1.00
25/05/2007
1/70
Page 3.1

Advertisement

loading

Related Manuals for FLY SDP100

Summary of Contents for FLY SDP100

  • Page 1 ANUAL Baseband section This document provides a description of the baseband section of the SDP100. Most design decisions are explained, but no detailed calculations are included. Total chip solutions(MT6228, MT6305BN, MT6120) except for RF Power Amplifier(RF3166) are from MediaTek, Taiwan.
  • Page 2 -. Real Time Clock(RTC) operating with a separate power supply. -. General Purpose I/Os (GPIOs) -. 2sets of Pulse Width Modulation(PWM) output. -. Alerter Output with enhanced PWM or PDM. -. 8 external interrupt lines. Security -. Cipher : supports AES, DES/3DES SDP100 T Page 3.2 ECHNICAL ANUAL...
  • Page 3 -.Multi-band Support (GSM850, GSM900, DCS1800, PCS1900) Voice and Model Codec -. Dial tone Generation. -. Voice memo -. Noise reduction -. Echo suppression -. Advanced sidetone Oscillation Reduction. -. Digital side-tone generator with programmable gain. SDP100 T Page 3.3 ECHNICAL ANUAL...
  • Page 4 -. Capable of processing image of size up to 3M pixels. -. Colour correction matrix. -. Gamma correction. -. Automatic exposure(AE) control. -. Automatic focus control. -. Automatic white balance(AWB) control. -. Programmable AE/AEB windows. SDP100 T Page 3.4 ECHNICAL ANUAL...
  • Page 5 -. Pixel processing : hue/saturation/intensity/color adjustment, Gamma correction and grayscale/invert/sepia-tone effects. -. Programmable spatial filtering : linear filter, non-linear filter and multi-pass artistic effects. -. Hardware accelerated image editing. -. Photo frame capability. -. RGB thumbnail data output. MPEG-4/H.263 CODEC SDP100 T Page 3.5 ECHNICAL ANUAL...
  • Page 6 Audio Interface and Audio Front End -. Supports I2S interface -. High resolution D/A Converters for Stereo Audio playback -. Stereo analog input for stereo audio source -. Analog multiplexer for stereo audio -. Stereo to mono conversion SDP100 T Page 3.6 ECHNICAL ANUAL...

  • Page 7: Product Description

    SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 7/70 UBJECT ECHNICAL ANUAL Figure 2 is shown the Block Diagram of MT6228 for detailly. Figure 2 : Block Diagram of MT6228 2. Product Description SDP100 T Page 3.7 ECHNICAL ANUAL...
  • Page 8 One type of Package for this product, TFBGA 13x13mm, 296balls, 0.65mm pitch package, is offered. Pin outs and the top view are illustrated in Figure 3,4. -. Pin Out Figure 3 . MT6228(7) Pin Out. -. Top and Bottom View SDP100 T Page 3.8 ECHNICAL ANUAL...
  • Page 9 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 9/70 UBJECT ECHNICAL ANUAL Top Masking Definition Figure 5. Top masking definition SDP100 T Page 3.9 ECHNICAL ANUAL...
  • Page 10 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 10/70 UBJECT ECHNICAL ANUAL Pin Description SDP100 T Page 3.10 ECHNICAL ANUAL...
  • Page 11 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 11/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.11 ECHNICAL ANUAL...
  • Page 12 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 12/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.12 ECHNICAL ANUAL...
  • Page 13 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 13/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.13 ECHNICAL ANUAL...
  • Page 14 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 14/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.14 ECHNICAL ANUAL...
  • Page 15 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 15/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.15 ECHNICAL ANUAL...
  • Page 16 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 16/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.16 ECHNICAL ANUAL...
  • Page 17 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 17/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.17 ECHNICAL ANUAL...
  • Page 18 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 18/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.18 ECHNICAL ANUAL...
  • Page 19 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 19/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.19 ECHNICAL ANUAL...
  • Page 20 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 20/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.20 ECHNICAL ANUAL...
  • Page 21 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 21/70 UBJECT ECHNICAL ANUAL SDP100 T Page 3.21 ECHNICAL ANUAL...
  • Page 22 32bit address space that has addressing capability up to 4GB. System RAM, System ROM , Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space, as depicted in Figure 7. SDP100 T Page 3.22...
  • Page 23 UART1 is used to configure the chip for factory programming. The Flash downloader program is then transferred into System RAM or external SRAM. Further information is detailed in the MT6228 Software Programming Specification. SDP100 T Page 3.23 ECHNICAL...
  • Page 24 MCU peripherals. Since ARM7EJ-S core supports two levels of interrupt latency, this controller generates two request signals: FIQ for fast, low latency interrupt request and IRQ for more general interrupts with lower priority. SDP100 T Page 3.24 ECHNICAL...
  • Page 25 The four external interrupts can be used for different kind of applications, mainly for event detections . In SDP100, External interrupts are used as followings. -. EINT 0 : TV Out cable and Headset Detection. -. EINT 1 : Folder On/Off -.
  • Page 26 The interface definition based on such a scheme is listed in Table 17. Note that, this interface always works with data in Little Endian format for all types of access. In SDP100, ECS0# is used for External SDRAM. The other ECSx# not used. Because of the Nand MCP used. SDP100 T Page 3.26...
  • Page 27 LCD backlight or charging purpose. The duration of the PWM output signal is low as long as the internal counter value is greater than or equal to the threshold value. In SDP100, PWM1 is used for LCD Module Backlight Enable and PWM2 is used for Flash LED Enable for GPIO mode. SIM Interface The MT6228 contains a dedicated smart card interface to allow the MCU access to the SIM card.
  • Page 28 Whenever the key status changes and is stable, a KEYPAD IRQ will be issued. The MCU can then read the key pressed directly in KP_HI_KEY, KP_MID_KEY and KP_LOW_KEY register. In SDP100, The 6 Rows are used (Row0 ~Row5) and The 5 Columns are used (Col 0~3 and Col 6) Figure 14. Key pressed with de-bounce mechanism SDP100 T Page 3.28...
  • Page 29 ECHNICAL ANUAL In SDP100, The 6 Rows are used (Row0 ~Row5) and The 5 Columns are used (Col 0~3 and Col 6) The 3x4 and Power On Keys are on Main Body. And Soft_Left/Right, Navy key are on Slide Body.
  • Page 30 The UART has M16C450 and M16550A modes of operation, which are compatible with a range of standard software drivers. In SDP100, UART1(URXD1, UTXD1) is used for Factory Programming and UART3(URXD3, UTXD3) is used for Blue Tooth Programming.
  • Page 31 3. The most recent CPU read of the FIFO was longer than four character periods ago IrDA SDP100 uses the HSDL-3208 IrDA Module. The HSDL-3208 is an ultra-small low cost infrared transceiver module that provides the interface between logic and infrared(IR) signals for through air, serial, half duplex IR data link. The Module is compliant to IrDA physical layer specifications version 1.4 Low Power from 9.6kbit/s to 115.2kbit/s with extended link...
  • Page 32 The Maximum day-of-month values, which depend on the leap year condition, are stored in the RTC block. In SDP100, Big Capacitor Battery(BAT300 TS414H) is used for Backup Battery. The Charging Voltage is about 1.5V by VRTC. The CM415DZF1 is a Cristal for 32.768Khz and The C100,C101 must be tuned.
  • Page 33 6.1 LCD Interface MT6228 contains a versatile LCD controller, which is optimized for multimedia applications. This controller supports many types of LCD modules and contains a rich feature set to enhance the functionality. These features are: SDP100 T Page 3.33 ECHNICAL ANUAL...
  • Page 34 -. /LPCE0/1 : Chip enable signal. -. NLD00 : 17 : data signal. SDP100 LCD uses the Hymax Driver IC HX8312 for 2.2” QVGA, 320x240 pixels 260Kcolors. Also, SDP100 LCD Module includes the followings. -. Key pad : soft left/right, OK, Navy key, Send and ESC.
  • Page 35 -. Used 7 control Signal : NRE#, NEW#,NCE#,NALE, WATCHDOG#,NCLE, NRNB. In SDP100, The Nand Flash Memory is used HYC0UEE0CF1 from Hynix. The HYC0UEE0CF1 is Nand Flash(512Mb) + SDRAM (256Mb). The Figure 23 is shown the Circuit diagram. The I/O is 8bit interface from MT6228.
  • Page 36 SDIO card specification version 1.0 partially. However, the controller can only be configured as either the host of Memory Stick or the host of SD/MMC Memory Card at one time. SDP100 is not interfaced Mini SD card but T-Flash Memory Card.
  • Page 37 R/G/B domain. The ISP is pipelined, and during processing stages ISP hardware can auto extract meaningful information for further AE/AF/AWB calculation. These information are temporary stored on ISP registers or memory and can be read back by MCU. SDP100 T Page 3.37 ECHNICAL...
  • Page 38 ECHNICAL ANUAL In SDP100, Camera Sensors can be selected by BB processor. If MT6228 is used, The Camera Module can be used 3Mpixels sensor from Micron (MT97012)., The 2 Power supplies are used(2.8V, 1.8V) and 10bit data interface. The I2C signals need a pull up resistor 10Kohm.

  • Page 39: Audio Front-End

    Figure 28. TV out Matching Circuit. So, SDP100 has a TV out function. The Figure 28 is a TV out matching circuit. The TV video cable is a 75ohm impedance and connected to I/O Connector CON40. The Audio Line is sharing with Melody Line.
  • Page 40 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 40/70 UBJECT ECHNICAL ANUAL Figure 29. Audio Front-End Block Diagram SDP100 T Page 3.40 ECHNICAL ANUAL...
  • Page 41 The ADC5_HF_MIC is for hook switch of Headset. If Hook is pressed, The ADC5_HF_MIC voltage is changed from 2.8V to The Figure 32 is shown the OPAmp circuit. The D-Class OPAmp was used which has a good PSRR for 217 GSM burst noise. The Output gain is 9 times by R600 and R603 resistor. SDP100 T Page 3.41 ECHNICAL...
  • Page 42 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 42/70 UBJECT ECHNICAL ANUAL Figure 32. Audio Amp Circuit Diagram. Figure 33. Mic Circuit diagram. SDP100 T Page 3.42 ECHNICAL ANUAL...
  • Page 43 0dBm and Sensitivity is about -80dBm. The distance during communication for Voice and Audio is around 13meter. BT Chip is BlueCore 3.So, If BT headset has a CSR Chip set, The paring is no problem. The BT Test is certificated in BQB. SDP100 T Page 3.43...
  • Page 44 6.3 FM Radio Stage. SDP100 Also, has a FM Radio chip set MT6188 from Media Tek. The interface is very simple. The FM_X1 frequency can be used 32Khz, 13Mhz and 26Mhz. The FM_X1 is from MT6228 GPIO port can be used for Oscillator output. The L80 is to tune the FM Radio band Q.
  • Page 45 The shape and magnitude of the ramp profiles are configurable to fit ramp-up, intermediate ramp, and ramp-down profiles. Each bank of the ramp profile consists of 16 8-bit unsigned values, which is adjustable for different conditions. SDP100 T Page 3.45...
  • Page 46 MT6228 Main system clock. If the VCTCXO output a frequency with much ppm , The Frequency error and Phase error are out of range. After calibrated, The Analog voltage is about 1.5V and AFC_DAC is about 4200 decimally. SDP100 T Page 3.46...

  • Page 47: Clocks And Reset

    UPLL : Provides the USB System Clock. Reset Generation Unit Figure 38 shows reset scheme used in MT6228. There are three kinds of resets in the MT6228, i.e., hardware reset, watchdog reset, and software resets. SDP100 T Page 3.47 ECHNICAL ANUAL...
  • Page 48 These are local reset signals that initialize specific hardware. For example, The MCU or DSP software may write to software reset trigger registers to reset hardware modules to their initial states, when hardware failures are detected. The following Modules has software resets DSP Core DSP Coprocessors. SDP100 T Page 3.48 ECHNICAL ANUAL...
  • Page 49 SIM Card interface Three Open-Drain Output Switches to Control the LED, Alerter and vibrator Thermal Overload Protection Under Voltage Lock-Out Protection Over Voltage Protection Power on Reset And start up Timer Figure 39. MT6305BN Pin configuration. SDP100 T Page 3.49 ECHNICAL ANUAL...
  • Page 50 UBJECT ECHNICAL ANUAL 1. Low Dropout Regulator and Reference The MT6305BNBN integrates seven LDOs that are optimized for their given functions by balancing quiescent current, dropout voltage, line/load regulation, ripple rejection, and output noise. SDP100 T Page 3.50 ECHNICAL ANUAL...
  • Page 51 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 51/70 UBJECT ECHNICAL ANUAL Figure 40. Functional Block Diagram of MT6305BN Figure 41. Status of Mobile Handset and LDOs. SDP100 T Page 3.51 ECHNICAL ANUAL...
  • Page 52 It provides level shifting needs for low voltage GSM controller to communicate with either 1.8V or 3V SIM cards. In SDP100, 3V SIM card is applied. All SIM cards contain a clock input, a reset input, and a bi-directional data input/output.
  • Page 53 10 LEDs simultaneously for backlight. The switch of vibrator can sink 250mA for a vibrator motor. The switch of alerter can sink 300mA to drive the beeper. And all the open-drain output switches are high impedance when disable. LED pin is dedicated to 7-colored indicator LED(In SDP100, dedicated to Slide Key BackLight LED), ALERTER pin is dedicated to Main KEY BackLight LED, VIBRATOR pin is dedicated to Vibrator Motor.
  • Page 54 Page is either 528 Bytes (512 + 16 spare) depending on whether the device has a x8 bus width. 256Mbit Low Power SDRAM(Mobile SDRAM) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organized as 4banks of 4,194,304x16. SDP100 T Page 3.54 ECHNICAL...
  • Page 55 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 55/70 UBJECT ECHNICAL ANUAL The devices are available in the following packages: 149-Ball P-FBGA Type - 10x14.0mm, 0.8mm pitch : Lead Free SDP100 T Page 3.55 ECHNICAL ANUAL...
  • Page 56 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 56/70 UBJECT ECHNICAL ANUAL 528M = 528 B 32 P 4,096 B LASH EMORY YTES X AGES X LOCKS Figure 45. Nand Flash Block diagram and Memory Cell SDP100 T Page 3.56 ECHNICAL ANUAL...
  • Page 57 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 57/70 UBJECT ECHNICAL ANUAL Organized as 4banks of 4,194,304x16 Figure 46. SDRAM Block diagram DC Operating Voltage DC Characteristics (Nand Flash Memory). VCC : 2.5V ~ 3.0V. SDP100 T Page 3.57 ECHNICAL ANUAL...
  • Page 58 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 58/70 UBJECT ECHNICAL ANUAL DC Characteristics (Mobile SDRAM). VDD/VDDQ : 1.7 ~ 1.95V SDP100 T Page 3.58 ECHNICAL ANUAL...
  • Page 59 RF section RF Section is combined with Transceiver MT6120, VCTCXO CSX-325T26, Power Amplier Module RF3166 and Front-End Module LMSP54HA-348(9). The SDP100 was designed for Tri-Band according to FEM, PCB Modify and S/W Matching. The one type is GSM900, DCS1800 an PCS1900 with LMSP54HA-348. Another type is GSM900, DCS1800 and PCS1900 with LMSP54HA-348.
  • Page 60 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 60/70 UBJECT ECHNICAL ANUAL Figure 47. MT6120 Functional block diagram Recommended Operating Range Item Symbol Unit Power Supply Voltage(VBAT) VBAT Power Supply Voltage(VCCD) VCCD Operating Ambient Temperature Topr SDP100 T Page 3.60 ECHNICAL ANUAL...

  • Page 61: Pin Description

    ERSION 25/05/2007 REPARED BY 61/70 UBJECT ECHNICAL ANUAL A description of MT612X hardware control pins and their functionality are shown in the table below. MT612X has an internal VCXO and its control. Pin Description SDP100 T Page 3.61 ECHNICAL ANUAL...
  • Page 62 Compared to a direct conversion receiver(DCR), MT6120’s very low-IF architecture improves the blocking rejection, AM suppression, as well as the adjacent channel interference performance. Receiver Input Frequency Mode Unit GSM850 GSM900 SDP100 T Page 3.62 ECHNICAL ANUAL...
  • Page 63 The TX VCO output is fed to the power amplifier. A control loop, implemented externally, is used to control the PA’s output power level. Transceiver Output Frequency Mode Unit GSM850 GSM900 1710 1785 1850 1910 3. TX VCO SDP100 T Page 3.63 ECHNICAL ANUAL...

  • Page 64: Frequency Synthesizer

    3-wire serial interface, the calibration loop is activated. The main function of the calibration loop is to preset the RF VCO to the vicinity of the desired frequency quickly and correctly, thus aiding the PLL to SDP100 T Page 3.64...
  • Page 65 26Mhz. When VCXOFRQ pin is low, Output Frequency is 13Mhz. VCXOFRQ is high in SDP100. The Amplifier is designed to be in series resonance with a standard 26Mhz crystal. The Crystal is connected from the Input pin XAL of Amplifier to ground through a series load capacitance. The buffer provides a typical 600mVpp voltage swing.
  • Page 66 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. SDP100 T Page 3.66 ECHNICAL...
  • Page 67 SDP100 V_1.00 ODEL ERSION 25/05/2007 REPARED BY 67/70 UBJECT ECHNICAL ANUAL Figure 49. Power control sequence SDP100 T Page 3.67 ECHNICAL ANUAL...
  • Page 68 The 3’rd BSI(ST3) is used to force RF module to terminate transmission and enter idle mode. All bands share the same timing but could has different HW control signals. SDP100 T Page 3.68 ECHNICAL...
  • Page 69 The Control Pins Operating range is 2.4V ~ 2.8V. LB_TX : GSM900 TX Enable. HB_TX : DCS1800, PCS1900 TX Enable. PCS_RX : PCS RX Enable. Figure 50. The Evaluation board of LMSP54HA-349 SDP100 T Page 3.69 ECHNICAL ANUAL...
  • Page 70 RF Component. The 2’nd BPI(PR2) is used to control antenna switch depend on its band. The 2’rd BPI(PR3) is used to force RF Module entering idle mode. All bands(GSM/DCS/PCS) share the same timing but could have different HW control signals. SDP100 T Page 3.70 ECHNICAL...