Seco Q7-A75-J User Manual page 36

Module with nxp i.mx6 processor
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Port
MXM
MXM Pin Name
#
Pin
99
eDP0_TX0+/LVDS_A0+
100
eDP1_TX0+/LVDS_B0+
101
eDP0_TX0-/LVDS_A0-
102
eDP1_TX0-/LVDS_B0-
103
eDP0_TX1+/LVDS_A1+
104
eDP1_TX1+/LVDS_B1+
105
eDP0_TX1-/LVDS_A1-
106
eDP1_TX1-/LVDS_B1-
107
eDP0_TX2+/LVDS_A2+
108
eDP1_TX2+/LVDS_B2+
109
eDP0_TX2-/LVDS_A2-
21
110
eDP1_TX2-/LVDS_B2-
111
LVDS_PPEN
112
LVDS_BLEN
113
eDP0_TX3+/LVDS_A3+
114
eDP1_TX3+/LVDS_B3+
115
eDP0_TX3-/LVDS_A3-
116
eDP1_TX3-/LVDS_B3-
119
eDP0_AUX+/LVDS_A_CLK+
120
eDP1_AUX+/LVDS_B_CLK+
121
eDP0_AUX-/LVDS_A_CLK-
122
eDP1_AUX-/LVDS_B_CLK-
123
LVDS_BLT_CTRL/GP_PWM_OUT0
126
eDP0_HPD#/LVDS_BLC_DAT
22
128
eDP1_HPD#/LVDS_BLC_CLK
μQ7-A75-J
μQ7-A75-J User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.B. - Reviewed by P.Z. - Copyright © 2016 SECO S.r.l.
®
Qseven
i.MX6 Signal
i.MX6 Pad
function
for standard
name
group
function
LVDS0_TX0_P
LVDS0_DATA0_P
LVDS1_TX0_P
LVDS1_DATA0_P
LVDS0_TX0_N
LVDS0_DATA0_N
LVDS1_TX0_N
LVDS1_DATA0_N
LVDS0_TX1_P
LVDS0_DATA1_P
LVDS1_TX1_P
LVDS1_DATA1_P
LVDS0_TX1_N
LVDS0_DATA1_N
LVDS1_TX1_N
LVDS1_DATA1_N
LVDS0_TX2_P
LVDS0_DATA2_P
LVDS1_TX2_P
LVDS1_DATA2_P
LVDS0_TX2_N
LVDS0_DATA2_N
LVDS Dual
Channel 24
LVDS1_TX2_N
LVDS1_DATA2_N
bit
LVDS_PPEN
GPIO_4
NANDF_CS0
LVDS_BLEN
LVDS0_TX3_P
LVDS0_DATA3_P
LVDS1_TX3_P
LVDS1_DATA3_P
LVDS0_TX3_N
LVDS0_DATA3_N
LVDS1_TX3_N
LVDS1_DATA3_N
LVDS0_CLK_P
LVDS0_CLK_P
LVDS1_CLK_P
LVDS1_CLK_P
LVDS0_CLK_N
LVDS0_CLK_N
LVDS1_CLK_N
LVDS1_CLK_N
GPIO_9
PWM1_OUT
GPIO_8
---
---
GPIO_7
---
i.MX6 Alternative Signal
WDOG1_B
FLEXCAN1_RX
I2C4_SDA
FLEXCAN1_TX
I2C4_SCL
Also
used in
Port #
GPIO1_IO04
GPIO6_IO11
GPIO1_IO09
GPIO1_IO08
GPIO1_IO07
36

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