Time Update Interrupt Function - Epson RX801SJ Applications Manual

Real time clock module
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RX8010 SJ

13.4. Time Update Interrupt Function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to
the timing of the internal clock. This /IRQ1 status is automatically cleared
13.4.1. Related registers for time update interrupt functions.
Address [h]
1D
Extension Register
1E
1F
∗ Before entering settings for operations, we recommend writing a "0" to the UIE bit to prevent hardware interrupts
from occurring inadvertently while entering settings.
∗ When the STOP bit value is "1" time update interrupt events do not occur.
∗ Although the time update interrupt function cannot be fully stopped, if "0" is written to the UIE bit, the time update
interrupt function can be prevented from changing the /IRQ1 pin status to low.
1) USEL bit ( Update Interrupt Select )
This bit is used to select "second" update or "minute" update as the timing for generation of time update
interrupt events.
USEL
Write
2) UF bit ( Update Flag )
This flag bit value changes from "0" to "1" when a time update interrupt event occurs.
UF
Write
Read
3) UIE bit ( Update Interrupt Enable )
This bit selects whether to generate an interrupt signal or to not generate it.
UIE
Write / Read
Function
bit 7
FSEL1
Flag Register
Control Register
TEST
Data
Selects "second update" (once per second) as the timing for generation of
0
interrupt events
Selects "minute update" (once per minute) as the timing for generation of
1
interrupt events
Data
Clearing this bit to zero enables /IRQ1 low output to be canceled
0
(/IRQ1 remains Hi-z) when an time update interrupt event has occurred.
1
This bit is invalid after a "1" has been written to it.
0
Time update interrupt events are detected.
1
(The result is retained until this bit is cleared to zero.)
Data
1) Does not generate an interrupt signal. (/IRQ1 remains Hi-z)
0
2) Cancels interrupt signal triggered by time update interrupt event (/IRQ1
changes from low to Hi-z).
1
When an Update interrupt event occurs, an interrupt signal is generated.
bit 6
bit 5
bit 4
FSEL0
USEL
TE
UF
TF
STOP
TIE
UIE
Description
Description
Description
Page − 23
bit 3
bit 2
bit 1
WADA TSEL2 TSEL1 TSEL0
AF
VLF
AIE
TSTP
-
ETM37E-06
bit 0
-

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