ST STM32L4P5AG User Manual page 14

Resistor
R37 and R38
1. The default configuration is shown in bold.
6.6 Audio (Footprint only)
A Cirrus codec CS42L51-CNZ, connected to the SAI interface of STM32L4P5AGI6PU, offers the possibility to
connect a stereo headphone or headset with a mono analog microphone. The codec communicates with
STM32L4P5AGI6PU via the I2C1 bus, which is shared with MFX and JDI LCD.
The I²C-bus addresses of CS42L51-CNZ are 0x95 and 0x94.
6.7 Digital microphones (Footprint only)
Two ST-MEMS IMP34DT05TR digital microphones, U17 and U23, are available on STM32L4P5G-DK. The two
microphones are located at a distance of 21 mm from each other. They are connected to the STM32 DFSDM by
the PE9 port, generating the clock, and by PD3 port, collecting the PDM interleaved data.
6.8 USB FS port
The STM32L4P5G-DK Discovery kit supports USB OTG FS, full-speed communication, via the CN7 USB Micro-
AB receptacle and U7 USB power switch connected to V
An LD7 green LED lits up in one of the following cases:
• The U7 power switch is ON and STM32L4P5G-DK works as a USB host.
• V is powered by another USB host when STM32L4P5G-DK works as a USB device.
BUS
The LD6 red LED is lit in case of overcurrent.
6.9 User LEDs
Two general-purpose color LEDs, LD1 and LD2, are available as light indicators. Each LED is in light-emitting
state with a low level of the corresponding ports of the STM32L4P5AGI6PU MCU.
6.10 Physical input devices
The STM32L4P5G-DK board provides a number of input devices for physical human control.
• A four-way joystick controller with select key (B1)
• A reset button (B2)
6.11 Octo-SPI device
U12, a 512-Mbit Octo-SPI user Flash memory MX25LM51245GXDI00 from MACRONIX, is connected to the
OCTOSPIM_P2 interface of STM32L4P5AGI6PU.
U11, a 64-Mbit Octo-SPI PSRAM memory APS6408L-3OBx-BA from APMemory, is connected to the
OCTOSPIM_P1 interface of STM32L4P5AGI6PU.
By default, U14 is the footprint of a Quad-SPI interface for the SO8 package, like APMemory APS1604M-3SQR-
SN. Note that U11 and U14 share the same GPIO port for Octo-SPI and Quad-SPI interface usage.
6.12 eMMC
The STM32L4P5G-DK Discovery kit embeds a 4-Gbyte eMMC chip. It is connected to the STM32L4P5AGI6PU
SDMMC1 port.
UM2651 - Rev 2
Table 5.
(1)
Setting
R37 OFF
R38 ON
R37 ON
R38 OFF
Boot selection switch
BOOT0 line is tied LOW. STM32L4P5AGI6PU boots from Main Flash
memory.
BOOT0 line is tied HIGH. STM32L4P5AGI6PU boots from system Flash
memory (nBOOT1 bit of FLASH_OPTR register is set HIGH) or from RAM
(nBOOT1 is set LOW).
.
BUS
Audio (Footprint only)
Description
UM2651
page 14/37