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47
H11T
EFMPLL VCO Interface
48
EFMPLLV DD
49
EFMVCOIN
50
EFMPLLV SS
51
EFMLPFGND
DLL (Delay Lock Loop) Interface
52
DLLV SS
53
DLLV DD
DAC Interface
54
DACVDD
55 ~ 58
DAC_OUT0 ~
DAC_OUT3
59
DACVSS
ADC Interface
61, 62, 63
ADC_IN0 ~
ADC_IN2
66
REFT
64, 65
ADCVDD1,
ADCVDD2
60, 67
ADCVSS1,
ADCVSS2
Reference Voltage Interface
68
BGVSS
69
VREFO
70
V2REFO
71
BGVDD
DMO Interface
73
RDMO_IN
74
WMDO
Miscellaneous Interface
76
PRST#
77
TEST_MODE
80, 82
FLAG_8,
FLAG_7
40
TTL Output,
EFM 11T indicator for ROPC sampling.
Slew rate
Analog VDD
Power pin for EFMPLL VCO circuitry.
Analog input
EFMPLL VCO input.
Analog VSS
Ground pin for EFMPLL VCO circuitry.
Analog input
EFMPLL LPF ground input.
Analog Ground
Ground pin for DLL circuitry.
Analog Power(5V)
Power pin for DLL circuitry.
Analog Power(5V)
Power pin for DAC circuitry.
Analog output
DA converter output. (10-bit resolution)
Analog Ground
Ground pin for DAC circuitry.
Analog Input
AD converter inputs that want to perform analog to digital
conversion. (8-bit resolution)
Analog Output
ADC reference ladder top.
Analog Power(5V)
Power pin for ADC circuitry.
Analog Ground
Ground pin for ADC circuitry.
Analog Ground
Ground pin for reference voltage generation circuitry.
Analog output
2V reference voltage output.
Analog output
4V reference voltage output.
Analog Power(5V)
Power pin for reference voltage generation circuitry.
Analog input
Reading path DMO input from DSP.
Analog output
Spindle motor PWM control output.
CMOS Input, SMT
Power on reset input, low active.
TTL Input,
Test mode enable pin, high active. A logical high sets MT1501
50K pull-down
enter test mode. An internal pull-down resistor sets MT1501 in
normal operation mode when this pin is floating.
TTL I/O,
Internal flag monitor output.
nd
Slew rate,
2
function : GPIO function.
rd
50K pull-up
3
function : External ADC interface
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