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118
IORDY
119
DMACK#
120
INTRQ
121
IOCS16#
124
PDIAG#
126, 123, 125 HA2, HA0, HA1
128
CS1FX#
129
CS3FX#
130
DASP#
132
DEVSEL
Buffer Memory Interface
141
BA1
142
BA0
153
DQML
42
I/O Channel Ready. Ultra DMA ready. Ultra DMA data strobe.
TTL Output, SMT,
For I/O channel Ready, this signal is negated to extend the host
Slew rate, PDR
transfer cycle of any register read or write when the device is not
able to complete the transfer.
For Ultra DMA Ready, this signal is asserted by the device to
indicate to the host that the device is ready to receive Ultra DMA
data out bursts from the host.
For Ultra DMA data strobe, this is the data in strobe signal from
device for Ultra DMA data in burst to the host.
TTL Input, SMT,
DMA Acknowledge. This signal shall be used by the host in
50K pull-up
response to DMARQ to acknowledge that it is ready for DMA
transfers.
TTL I/O,
Device Interrupt. This signal is used to interrupt the host system.
Slew rate
INTRQ is driven only when this chip is addressed. When not
driven, INTRQ is in a high impedance state.
TTL Output,
Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16#
Open-Drain
indicates to the host system that the 16-bit data port has been
addressed and that the device is prepared to send or receive a
16-bit data word.
TTL I/O,
Passed Diagnostics. This signal is asserted by Device 1 to
50K pull-up
indicate to Device 0 that it has completed diagnostics.
TTL Input, SMT,
Device Address. This is the 3-bit binary coded address provided
50K pull-up
by the host to access an ATA register or data.
TTL Input, SMT,
Device Chip Select 0 (for 1Fxh/17xh). This is the chip select signal
50K pull-up
from the host to select the Command Block Registers.
TTL Input, SMT,
Device Chip Select 1 (for 3Fxh/37xh). This is the chip select signal
50K pull-up
from the host to select the Control Block Registers.
TTL I/O,
Device Active / Device 1 Present. This is a time-multiplexed signal
50K pull-up
that indicates that a device is active, or that Device 1 is present.
TTL Input, SMT,
Device Select. Cleared to zero indicates the driver is master
50K pull-up
device. Set to one indicates the driver is slave device.
3.3V CMOS
SDRAM bank address 1 signal. For SDRAM application only.
Output,
When 4-bank SDRAM is used, this pin is used to select bank2 and
Slew rate, PDR
bank3 space and musts connect to "BA1" pin of SDRAM.
When two 2-bank SDRAM are used, this pin is used as "Chip
Select" signal output for second SDRAM and musts connect to
"CS#" pin of second SDRAM.
3.3V TTL Output,
SDRAM bank address 0 signal. For SDRAM application only.
Slew rate, PDR
2
3.3V CMOS
SDRAM low-byte data output mask control signal, high active. For
Output,
SDRAM application only.
3
Slew rate, PDR
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