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PIN DESCRIPTION
Pin Numbers
Symbol
DSP interface
2
C2PO
3
SBSO
4
WFCK
5
SUB
6
EXCK
8
FG
12
TRON_IN
13
HRFZC
205
DSP_CS#
206
LRCK
207
SDATA
208
BCK
Audio Output Interface
9
ABCK
10
ALRCK
11
ASDATA
194
ACLK
134
ADGO
Write Strategy Interface
14
WSR_ENBL
38
Type
Description
TTL Input, SMT,
C2 error pointer. Active high when errors occur after CIRC C2
50K pull-up
correction.
TTL Input, SMT,
Subcode serial data input. Supplies the serial Subcode data from
50K pull-up
DSP. The Subcode is stored in the order of P–W.
TTL Input, SMT,
Subcode frame clock input. The active-high signal is used to
50K pull-up
indicator the Subcode frame header.
TTL Input, SMT,
Subcode sync input. The active-high signal indicates the position
50K pull-up
of a Subcode SYNC pattern.
TTL Input, SMT,
External clock. This input signal is a clock from the DSP for
50K pull-up
reading the serial Subcode data.
TTL Input, SMT,
Motor Hall sensor input.
50K pull-up
TTL Input, SMT,
On track indicator. The active-high input signal is a indicator used
50K pull-up
to point the tracking servo is on track.
TTL Output,
RF ripper zero crossing signal output.
Slew rate
TTL Output
DSP chip select.
TTL Input, SMT,
L/R channel indicator. A logical low indicates L channel 16-bit data
50K pul -up
and high indicates R channel 16-bit data.
TTL Input, SMT,
Serial data input. The serial input is used for receiving the digital
50K pull-up
data after CIRC correction of DSP.
TTL Input, SMT,
Bit clock input. The signal clocks the serial data on the SDATA
50K pull-up
input. Proper synchronization between LRCK and BCK is
necessary.
TTL Output
Audio bit clock output. The signal clocks the serial data on the
ASDATA output. Data on the ASDATA signal shall be latched by
an audio DAC at the rising edge of ABCK.
TTL Output
Audio L/R channel indicator. The signal is the audio left and right
channel clock which indicates the data on ASDATA is from left or
right channel.
TTL Output
Audio serial data output. The signal is the audio serial data output
which supplies the serialized audio sample.
TTL I/O
DSP main clock input or output. (33.8688M Hz)
The ACLK function is determined by the "AGCON" status during
power-on stage. And can be changed by the "ACLKOUT_SEL" bit
of ATIP "MISCCTL" (0x70) command.
TTL I/O, SMT,
Digital Audio Output. The signal is the Digital Audio Output which
Slew rate,
supplies the IEC-958 digital audio data.
50K pull-up
Alternate function :
stage. A logical low input indicates an address/data bus separated
type CPU (eg. H8) is used. A logical high input indicates an
address/data bus multiplexed type CPU (eg. 8051, 8032) is
implemented.
CMOS Output
Laser diode enable signal output
.
CPU type selection input during power-on
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