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Phytec phyCORE-LPC2292/94 Hardware Manual

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phyCORE-LPC2292/94
Hardware Manual
Edition July 2006
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-LPC2292/94

  • Page 1 Hardware Manual Edition July 2006 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Contents Preface......................1 Introduction..................3 1.1 Block Diagram ................6 1.2 View of the phyCORE-LPC2292/94 ........... 7 Pin Description ..................9 Jumpers....................17 3.1 J200, J202 Second Serial Interface ........... 24 3.2 J201, J203 First Serial Interface..........25 3.3 J204 A/D Converter ..............26 3.4 J205, J206 Chip Select Configuration........
  • Page 4 Battery Buffer ................... 63 Debug Interface X701............... 65 debugCORE-LPC2292/94..............69 Technical Specifications ..............73 Hints for Handling the phyCORE-LPC2292/94......75 The phyCORE-LPC2292/94 on the phyCORE Carrier Board HD200 ..................77 16.1 Concept of the phyCORE Carrier Board HD200 ...... 77 16.2 Carrier Board HD200 Connectors and Jumpers ......
  • Page 5 Contents Ethernet Port ................... 121 Revision History ................123 Component Placement Diagram............ 125 Index......................127 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 6 Index of Figures Figure 1: Block Diagram phyCORE-LPC2292/94 ........6 Figure 2: Top View of the phyCORE-LPC2292/94 ......... 7 Figure 3: Bottom View of the phyCORE-LPC2292 ......... 8 Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross Section Insert) ................11 Figure 5: Numbering of the Jumper Pads..........
  • Page 7 Figure 23: Pin Assignment of the DB-9 Socket P1B as Second RS-232 (Front View)........... 93 Figure 24: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on phyCORE-LPC2292/94, Front View) ........ 95 Figure 25: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Carrier Board) ..............96 Figure 26: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Carrier Board with Galvanic Separation) ......
  • Page 8 J616, J617 CAN Transceiver VCC at Pin #5 ......42 Table 30: J618 VDD_V3V3 Supply Control.......... 43 Table 31: J619, J620 SPI Master/Slave Selection ........43 Table 32: J621 WDI Signal Source ............44 Table 33: J622 RESET Signal Source ............ 45 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 9 JP24 Power Supply to External Devices Connected to P1A on the Carrier Board............92 Table 54: Jumper Configuration of the DB-9 Socket P1B (Second RS-232) ..............93 Table 55: Improper Jumper Settings for DB-9 Socket P1B (Second RS-232) ..............94 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 10 JP17 Configuration of the Programmable LED D3....107 Table 68: JP40 Configuration of User Button S3 ......... 107 Table 69: Pin Assignment Data Bus for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board .......... 110 Table 70: Pin Assignment Address Bus for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board..............
  • Page 11 Contents Table 73: Pin Assignment Port P1 for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board........... 114 Table 74: Pin Assignment Interface Signals for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board ..............115 Table 75: Pin Assignment Power Supply for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board ..............
  • Page 12 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 13: Preface

    (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m. © PHYTEC Messtechnik GmbH 2006...
  • Page 14 The phyCORE-LPC2292/94 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports...

  • Page 15: Introduction

    The phyCORE-LPC2292/94 is a subminiature (60 x 53 mm) insert- ready Single Board Computer populated with the Philips LPC2292/94 microcontroller. Its universal design enables its insertion in a wide range of embedded applications.
  • Page 16 C Real-Time Clock with internal quartz (can be battery buffered) • up to two free microcontroller Chip Select signals (if optional Ethernet controller is not populated) Please contact PHYTEC for more information about additional module configurations. © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 17 <12 mA • support of LPC2292/2294 single chip mode • support of ETM debug interface (only on debugCORE version) Please contact PHYTEC if you have questions about changing the CPLD code. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 18: Block Diagram

    CAN1 CAN1H / CAN1L C A N Transceiver digital I / O ports SPI bus Reset JTAG/ETM Connector E E P R O M R e s e t Figure 1: Block Diagram phyCORE-LPC2292/94 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 19: View Of The Phycore-Lpc2292/94

    Introduction 1.2 View of the phyCORE-LPC2292/94 X200 U303 U301 U300 U302 RN200 U401 U403 U400 U402 U600 U605 U606 U201 Q200 XT500 XT200 X701 Figure 2: Top View of the phyCORE-LPC2292/94 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 20: Figure 3: Bottom View Of The Phycore-Lpc2292

    U601 U607 U603 Q600 RN601 U602 U202 RN201 U200 RN501 RN502 U608 RN503 U501 RN504 U500 RN500 RN600 X700 U203 U604 RN700 Figure 3: Bottom View of the phyCORE-LPC2292 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 21: Pin Description

    PHYTEC Carrier Board or in user target circuitry. The numbering scheme for the phyCORE-connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number.
  • Page 22 Carrier Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner of the phyCORE-LPC2292/94 marked with a white triangle. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

  • Page 23: Figure 4: Pinout Of The Phycore-Connector (Top View, With Cross Section Insert)

    Pin Description The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-LPC2292/94 with SMT phyCORE- connectors on its underside (defined as dotted lines) mounted on a Carrier Board. In order to facilitate understanding of the pin...
  • Page 24 I/O Freely programmable PLD signal (may be used as additional Chip Select signal) /BLS2 Low active Byte Lane Select signal (Bank2) 48A, 49A, P03, P05, I/O Port 0 of the microcontroller (see corresponding Data Sheet) © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 25 BOOT Boot input of the phyCORE module, switches controller into boot mode during reset /RESET /RESET output of the phyCORE-LPC2292/94 I/O Freely programmable PLD signal (may be used as additional Chip Select signal) P010 I/O Port P010 of the microcontroller (see data sheet)
  • Page 26 Freely programmable PLD signal (may be used as additional Chip Select signal) TMS_PLD JTAG Scan Chain TMS Signal from the PLD 48C, 49C, P030, P028, Port P0 of the microcontroller, P027 alternative: analog inputs AIN0, AIN1, AIN3 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 27 Output of back-up voltage supply for buffering of external components MAX6301 Watchdog input /RESIN /RESET input of the phyCORE-LPC2292/94 TxD1 Output of the second serial interface, TTL level (alternative: port P08 of the microcontroller) RxD1 Input of the second serial interface, TTL level...

  • Page 28: Table 1: Pinout Of The Phycore-Connector X1

    JTAG Scan Chain TDO signal from the PLD 44D, 49D VAGND Analog Ground P029 Port P029 of the microcontroller (see data sheet) ADVREF Reference voltage input for A/D converter Table 1: Pinout of the phyCORE-Connector X1 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 29: Jumpers

    Jumpers 3 Jumpers For configuration purposes, the phyCORE-LPC2292/94 has 51 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the jumper pads, while Figure 6 and Figure 7 indicate the location of the jumpers on the board. With the exception of J619, J620 and J22, all other solder jumpers are located at the top side (microcontroller side) of the module.

  • Page 30: Figure 7: Location Of The Jumpers (Bottom View)

    U607 U601 U603 Q600 RN601 J622 U202 RN201 U200 RN501 RN502 RN503 U501 J620 RN504 J619 RN500 X700 RN600 U604 RN700 Figure 7: Location of the Jumpers (Bottom View) © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 31 2 of CPLD U202 of the CPLD connected to connected to VCC via 10k pull-up Applies to standard modules without optional features, minimal memory configuration. Default on all other configuration options of the phyCORE-LPC2292/94. © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 32 Molex pins X700A6 and B6. J503 open P018 from the µC freely closed P018 used to supervise the available at X700C16. Ready signal on the on SMSC LAN91C111. P018 is then no longer available at Molex pin X700C16. © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 33 CAN transceiver U605 connected with µC port TD1 and (only if CAN transceiver available as CAN TTL signal an U605 populates the module). X700D21, for connection to external CAN transceiver (only in connection with unpopulated U605). © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 34 µC on the module, the µC. P03 is then no external connection required (at longer available as standard pin X700D32). P03 is available I/O pin at X700A48. as standard I/O pin at X700A48. © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 35 3.3 V supply supply voltage (use only voltage (use only with other with TLE6250V33 devices) CAN transceivers). J618 open VDD_V3V3 supply voltage closed VDD_V3V3 supply voltage is switched via FET Q600A. directly derived from VCC. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 36: J200, J202 Second Serial Interface

    X700C21 and X700C23. If the jumpers are closed at position 1+2 we recommend not to use the interface signals with their TTL level as this will cause damage to the on-board components. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 37: J201, J203 First Serial Interface

    I/O pin at X700D22 and X700D23 P00 and P01 as I/O pin or TxD0 and open open RxD0 interface signals with TTL level at X700D16 and X700D17 * = Default setting Table 4: J201, J203 First Serial Interface Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 38: J204 A/D Converter

    J204 A/D Converter Reference Voltage J205, J206 Chip Select Configuration If the phyCORE-LPC2292/94 is delivered with the minimum memory configuration, then the CPLD device is not required. In this case Jumper J205 and J206 must be closed in order to connect the Chip Select signals for Flash and SRAM with the corresponding controller signals.

  • Page 39: J207 Mcko Signal

    µC (/CS0 and /CS1) * Note: If minimum configuration of the phyCORE-LPC2292/94 is used these jumpers must be closed Table 6: J205, J206 Chip Select Configuration 3.5 J207 MCKO Signal This jumper can be used to connect the master clock output signal (MCKO) to Molex pin X700B1 for use in external application circuitry.

  • Page 40: J208, J209 Flash Size Configuration

    3.6 J208, J209 Flash Size Configuration The phyCORE-LPC2292/94 can be populated with three different Flash memory sizes per shape (U300 thru U303). The size of the device must be configured to ensure linear addressing of the entire Flash bank. Jumpers J208 and J209 are used to select the size of the memory device.

  • Page 41: J210, J211 Ram Size Configuration

    Jumpers 3.7 J210, J211 RAM Size Configuration The phyCORE-LPC2292/94 can be populated with three different RAM memory sizes per shape (U400 thru U403). The size of the device must be configured to ensure linear addressing of the entire RAM bank. Jumpers J210 and J211 are used to select the size of the memory device.

  • Page 42: J300 Flash Ready/Busy Configuration

    P017 used to supervise the Ready/Busy outputs of both closed Flash banks U300/U301 and U302/U303, P017 not available as standard I/O at Molex pin X700D15 * = Default setting Table 10: J300 Flash Ready/Busy Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 43: J301, J302 Flash Write Protection Configuration

    Flash bank U302/U303 without hardware don't care open* write protection Flash bank U302/U303 with hardware don't care closed write protection * = Default setting Table 11: J301, J302 Flash Write Protection Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 44: J400, J401 Sram Configuration

    Jumpers J400 and J401 are required for configuring the SRAM signals /BLS0 through /BLS3. This configures the controller access to the various SRAM types that populated phyCORE-LPC2292/94, since these can have various data bus configurations. The following configurations are possible: Signal Configuration J400 J401 1 + 2 *...

  • Page 45: J500 Through J509 Ethernet Controller Smsc Lan91C111Configuration

    J500 through J509 Ethernet Controller SMSC LAN91C111Configuration As an option, a LAN91C111 Ethernet controller from SMSC can populate the phyCORE-LPC2292/94 at U501. If the Ethernet controller populates the phyCORE module, one of two possible Chip Select signals for controlling access to the LAN91C111 can be selected using Jumper J502.

  • Page 46: Table 16: J503 Ethernet Ready Signal Configuration

    VDD_V3V3, configuration via predefined EEPROM contents IOSx signal on LAN 91C111 connected closed closed closed to GND (see data sheet for details) * = Default setting Table 18: J505, J506, J507 Ethernet EEPROM Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 47: Table 19: J508 Ethernet Eeprom Enable Configuration

    EPH status register is set to "1" LAN 91C111 nLNK pin not connected, LINK_ON bit in open the EPH status register is set to "0" * = Default setting Table 20: J509 Ethernet nLNK Pin Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 48: J600, J601, J616 Can Transceiver Configuration

    U606. Routing the VDD_V3V3 supply voltage to pin 5 of the relevant CAN transceiver is only required if the TLE 6250V3V3 populates the phyCORE module. If the Philips 82C251 CAN transceiver is populated, the jumper must be open. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 49: J602, J603, J604, J605 Can Interfaces

    J616 CAN Transceiver Supply Configuration 3.14 J602, J603, J604, J605 CAN Interfaces Two CAN interfaces are provided by the phyCORE-LPC2292/94. The CAN signals extend to the two TLE6250V33 CAN transceivers at U605 and U606. The CAN transceivers generate the corresponding CAN_H1, CAN_L1, CAN_H2 and CAN_L2 signals.

  • Page 50: J606 Write Protection Of Spi Eeprom

    Should only be used if CAN transceivers U605 and U606 are populated. Note! Should only be used if CAN transceivers U605 and U606 are NOT populated. Refer to the corresponding EEPROM Data Sheet for more information on the write protection function. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 51: J607 Watchdog Configuration

    WDT is disabled allowing unlimited use of the phyCORE module. Following RESET (without active low signals /BOOT and /DEBUG) the WDT is always enabled if Jumper J607 is closed. * = Default setting Table 25: J607 Watchdog Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 52: J608, J609, J610 I C Interface

    SPI0 bus connected closed* closed* closed* closed* (SCLK0, /PCS0 MISO0, MOSI0) on-board SPI0 bus disconnected open open open open * = Default setting Table 27: J611, J612, J613, J614 SPI Interface Signal Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 53: J615 Can Bus Level Configuration

    Pin 3 on CAN transceivers U605 and U606 not 2 + 3 connected to 3.3 V supply voltage VDD_V3V3 (use only with other CAN transceivers) * = Default setting Table 28: J615 CAN Level Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 54: J616, J617 Can Transceiver Vcc, Pin 5

    These jumpers are used to connect the 3.3 V main supply voltage to pin #5 on the TLE6250V33 CAN transceivers at U605 (J616) and U606 (J617). If other CAN transceiver devices are used on the phyCORE-LPC2292/94 these jumpers must remain open. The following configurations are possible: CAN Transceiver VCC, Pin 5...

  • Page 55: J618 Vdd_V3V3 Supply Control

    SPI0 operates in Slave mode after RESET. closed SPI1 operates in Master mode after RESET. open* SPI1 operates in Slave mode after RESET. closed * = Default setting Table 31: J619, J620 SPI Master/Slave Selection © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 56: J621 Wdi Signal Source

    Jumper J622 configures the source of the high active RESET signal. Closing Jumper J622 (requires Q601 to not be populated) connects the output of U601 (TLC7701) with the RESET signal which allows push/pull generation of the high active RESET signal. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 57: J800, J801 Etm/Ocds Connector Configuration (Only With Debugcore-Lpc2292/94)

    Vsupply and VTREF on the ETM/OCDS 1 + 2* connector are supplied via VDD_V3V3 Vsupply and VTREF are connected to GND 2 + 3 * = Default setting Table 34: J800, J801 ETM/OCDS Connector Configuration (DCM-023 only) © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 58: C210 Clkin Configuration

    The following configurations are possible: CLKIN Configuration C210 Using the on-board crystal XT1 open* Supply via external clock signal at phyCORE 100p/50V capacitor connector pin X700A1 mounted * = Default setting Table 35: C210 CLKIN Configuration © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 59: System Configuration

    BOOT0 = 0 BOOT1 = 0 Internal Flash access unpopulated unpopulated BOOT0 = 1 BOOT1 = 1 Table 36: System Startup Configuration – Boot Device Selection Default system startup configuration on the phyCORE-LPC2292/94 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 60: Starting The Lpc2292/94 Isp Mode

    This is achieved by applying a high-level signal at pin X1C9 (BOOT) of the phyCORE-LPC2292/94. A transistor circuitry connects P0.14 to GND as long as the BOOT pin is high. An on-board pull-up resistor (R213) ensures a high level at P0.14 if the BOOT signal is not active.

  • Page 61: Memory Models

    Depending on the number of memory devices installed on the phyCORE-LPC2292/94, as well as the availability of the optional Ethernet controller, up to three Chip Select signals are used internally.
  • Page 62 /CS Signal (Bank) Address Ranges and Configuration Registers The following image depicts the default memory model on the Philips LPC2292/94 microcontroller showing internal and external address spaces of the controller. This memory model also applies to the phyCORE-LPC2292/94 module. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 63: Figure 8: Phycore-Lpc2292/94 Memory Model

    Standart write access : WST2 >= ((t – tcyc +5 ns) / t WRITE where = 1/ f = memory acces time read of external memory = memory access time write of external memory WRITE © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 64 Philips for more details on bus timing configuration. The following section contains two examples of the controller’s configuration registers. These examples match the needs of most standard applications for the phyCORE-LPC2292/94. Example a) Module Configuration: • Flash access time = 90 ns •...
  • Page 65 7 CCLK cycles BUSERR -> not relevant WPERR -> no write protection error -> bank not write protected -> no burst ROM bank -> 32-bit wide bus -> always write 0 to this field © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 66 4 CCLK cycles BUSERR -> not relevant WPERR -> no write protection error -> bank not write protected -> no burst ROM bank -> 32-bit wide bus -> always write 0 to this field © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 67: Serial Interfaces

    TxD line of the COM port; while the TxD line is connected to the RxD line of the COM port. The Ground potential of the phyCORE-LPC2292/94 circuitry needs to be connected to the applicable Ground pin on the COM port as well.

  • Page 68: Can Interface

    6.2 CAN Interface The phyCORE-LPC2292/94 is designed to house two CAN transceivers at U605 and U606 (either PCA82C251 or TLE6250V33). The CAN bus transceiver devices support signal conversion of the CAN transmit (CANTx) and receive (CANRx)lines. The CAN transceiver supports up to 110 nodes on a single CAN bus. Data transmission occurs with differential signals between CANH and CANL.

  • Page 69: Serial Eeprom (U607)

    Serial EEPROM 7 Serial EEPROM (U607) The phyCORE-LPC2292/94 is populated with a non-volatile memory with a serial interface (SPI interface) to store configuration data. According to the memory configuration of the module an EEPROM (1 to 8 kByte) can be mounted at U607. A description of the SPI protocol can be found in the applicable EEPROM Data Sheet.

  • Page 70: On-Board Flash Memory (U300-U303)

    RAM). This usually equals the interruption of a "normal" program execution cycle. If the phyCORE-LPC2292/94 is populated with multiple Flash devices on the available Flash banks it is possible to store application data in a Flash area which is physically seperated from the Flash area that contains program code.

  • Page 71: Lan91C111 Ethernet Controller (U501)

    The /CS signal for the LAN91C111 Ethernet controller at U501 can be connected to the LPC2292 processor's /CS2 or /CS3 signal using Jumper J502. The Ethernet controller's offset of 0x300 has to be noted when accessing the chip. © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 72: Mac Address

    MAC addresses and each one of our Ethernet-based Single Board Computers gets one of these addresses. The MAC address of your phyCORE-LPC2292/94 is printed on a barcode sticker attached to the module. The MAC address is provided as a 12-digit hexadecimal value.

  • Page 73: Ethernet Eeprom (U500)

    Please refer to the SMSC Ethernet controller datasheet for details on the external circuitry design. This circuitry is also available from PHYTEC on an Ethernet adapter module, order code EAD-003 (refer to section 17). © PHYTEC Messtechnik GmbH 2006...

  • Page 74: Real-Time Clock Rtc-8564 (U604)

    Real-Time Clock RTC-8564 (U604) For real-time or time-driven applications, the phyCORE-LPC2292/94 is equipped with a RTC-8564 Real-Time Clock at U604. This RTC device provides the following features: • Serial input/output bus (I C), address 0xA2 • Power consumption Bus active (400 kHz): <...

  • Page 75: Battery Buffer

    As of the printing of this manual, a lithium battery is recommended as it offers relatively high capacity at low discharge. In the event of a power failure at VCC, the RTC will be buffered by a connected battery via VBAT. The RTC is generally supplied via VPD in order to preserve data by means of the battery back-up in the absence of a power supply via VCC.
  • Page 76 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 77: Debug Interface X701

    Debug Interface 12 Debug Interface X701 The phyCORE-LPC2292/94 is equipped with a JTAG interface for downloading program code into the external Flash or for debugging programs in the external SRAM. The JTAG interface extends out to 2 mm pitch pin header rows X701 on the controller side of the module.

  • Page 78: Figure 11: Jtag Interface (Bottom View)

    On-board configuration resistors select if the corresponding port pins function as JTAG interface or as standard I/O port. In addition to the standard JTAG port the phyCORE-LPC2292/94 also features a TRACE port which is also configured via on-board resistors. Refer to section 13 for details.
  • Page 79 JTAG interface. See Table 74 for details on the JTAG signal pin assignment. PHYTEC offers a JTAG-Emulator adapter (order code JA-002) for connecting the phyCORE-LPC2292/94 to a standard emulator. The JTAG-Emulator adapter extends the signals of the module's JTAG connector to a standard ARM connector with 2.54 mm pin pitch.
  • Page 80 © PHYTEC Messtechnik GmbH 2006 L-658e_5...

  • Page 81: Debugcore-Lpc2292/94

    13 debugCORE-LPC2292/94 The debugCORE-LPC2292/94 is a special debugging version of the phyCORE-LPC2292/94 module. The debugCORE differs from its phyCORE counterpart, in that an additional debug interface and corresponding circuitry been added. debugCORE-LPC2292/94 there is also the possibility of connecting the MII interface of the LAN91C111 Ethernet controller.

  • Page 82: Figure 13: Debugcore-Lpc2292/94 (Bottom View)

    Port pins P116-P125 function as standard I/O function as Trace port port Port pins P126-P131 Port pins P126-P131 function as standard I/O function as debug interface port reserved reseverd Table 42: debugCORE-LPC2292/94 DIP Switch S800 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...
  • Page 83 Trace packet signal 1. TRACEPKT0 Trace packet signal 0. TRACESYNC Trace synchronization signal. PIPESTAT2 Pipe Line status signal 2. PIPESTAT1 Pipe Line status signal 1. PIPESTAT0 Pipe Line status signal 0. Table 43: ETM/OCDS Connector at X800 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 84 LAN_TXD3 Transmit data nibble to MII PHY, output LAN_COL Collision detect input from MII PHY. LAN_CRS Envelope of packet reception from MII PHY. 22, 23, 24 Ground Table 44: LAN MII Connector at X500 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 85: Technical Specifications

    Technical Specifications 14 Technical Specifications The physical dimensions of the phyCORE-LPC2292/94 are represented in Figure 14. The module's profile is ca. 7.2 mm thick, with a maximum component height of 2.6 mm on the bottom (connector) side of the PCB and approximately 3.0 mm on the top (microcontroller) side.
  • Page 86 CPU frequency at 20°C These specifications describe the standard configuration of the phyCORE-LPC2292/94 as of the printing of this manual. Please note that the module storage temperature is only 0°C to +70°C if a battery buffer is used for the RAM devices.

  • Page 87: Hints For Handling The Phycore-Lpc2292/94

    Hints for Handling 15 Hints for Handling the phyCORE-LPC2292/94 The address and data bus on the module is not buffered. To connect external components to the data/address bus, as well as the control lines (/RD, /WR), an external buffer (i.e. 74AHCT245) between the modul and the peripheral components should be installed.
  • Page 88 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 89: The Phycore-Lpc2292/94 On The Phycore Carrier Board Hd200

    The phyCORE-LPC2292/94 on the phyCORE Carrier Board The phyCORE-LPC2292/94 on the phyCORE Carrier Board HD200 PHYTEC Carrier Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules.

  • Page 90: Figure 15: Modular Development And Expansion Board Concept With The Phycore-Lpc2292/94

    • As the physical layout of the expansion bus is standardized across all applicable PHYTEC Carrier Boards, we are able to offer various expansion boards (5) that attach to the Carrier Board at the expansion bus connectors. These modular expansion boards offer...

  • Page 91: Carrier Board Hd200 Connectors And Jumpers

    The phyCORE-LPC2292/94 on the phyCORE Carrier Board 16.2 Carrier Board HD200 Connectors and Jumpers 16.2.1 Connectors As shown in Figure 16, the following connectors are available on the phyCORE Carrier Board HD200: low-voltage socket for power supply connectivity mating receptacle for expansion board connectivity...
  • Page 92 Sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 93: Jumpers On The Phycore Carrier Board Hd200

    16.2.2 Jumpers on the phyCORE Carrier Board HD200 Peripheral components of the phyCORE Carrier Board HD200 can be connected to the signals of the phyCORE-LPC2292/94 by setting the applicable jumpers. The Carrier Board's peripheral components are configured for use with the phyCORE-LPC2292/94 by means of insertable jumpers.

  • Page 94: Figure 19: Default Jumper Settings Of The Phycore Development Board Hd200 With Phycore-Lpc2292/94

    HD200 with standard phyCORE-LPC2292/94 (standard = LPC2292 controller, use of first and second RS-232 and CAN interfaces and LED D3 on the Carrier Board). Jumper settings for other functional configurations of the phyCORE-LPC2292/94 module mounted on the Carrier Board are described in section 16.3.

  • Page 95: Unsupported Features And Improper Jumper Settings

    DB-9 plug P2B on the Carrier Board can be configured as RS-485 interface as an alternative to the second CAN interface. The phyCORE-LPC2292/94 does not support an RS-485 interface. For this reason the corresponding jumper settings should never be used.

  • Page 96: Functional Components On The Phycore Carrier Board Hd200

    Permissible input voltage: +/-5 VDC regulated. The required current load capacity of the power supply depends on the specific configuration of the phyCORE-LPC2292/94 mounted on the Carrier Board as well as whether an optional expansion board is connected to the Carrier Board. An adapter with a minimum supply of 500 mA is recommended.

  • Page 97: Figure 20: Connecting The Supply Voltage At X1

    JP9, JP16 Improper Jumper Settings for the Main Supply Voltages Setting Jumper JP9 to position 2+3 configures a primary main power supply to the phyCORE-LPC2292/94 of 5 V which could destroy the module. Setting Jumper JP16 to position 1 + 2 configures a secondary main power supply to the phyCORE-LPC2292/94 of 3.3 V which also...

  • Page 98: Starting The Isp Command Handler

    P0.14 of the microcontroller must be connected to a low signal level at the time the Reset signal changes from its active to the inactive state. This is achieved by applying a high-level signal...
  • Page 99 The phyCORE-LPC2292/94 on the phyCORE Carrier Board 2. The Boot input of the phyCORE-LPC2292/94 can also be perma- nently connected to VCC via a pull-up resistor. This pulls port pin P0.14 to low level via on-board circuitry which then starts the ISP mode.

  • Page 100: Phycroe-Lpc2292/4 Boot Memory Configuration

    Flash. 2. Boot from on-board Flash (32-bit data bus width) connected to Chip Select /CS0 If R203 is not installed on the phyCORE-LPC2292/94 closing Jumper JP41 on the Carrier Board allows code execution from the on-board Flash connected to the LPC2292/94 via /CS0. This will result in a low signal level at data line D26 during a reset cycle.

  • Page 101: First Serial Interface At Socket P1A

    The phyCORE-LPC2292/94 on the phyCORE Carrier Board 16.3.4 First Serial Interface at Socket P1A Socket P1A is the lower socket of the double DB-9 connector at P1. P1A is connected via jumpers to the first serial interface of the phyCORE-LPC2292/94.
  • Page 102 Caution: When using the DB-9 socket P1A as RS-232 interface on the phyCORE-LPC2292/94 the following jumper settings are not functional and could damage the module: Jumper Setting Description JP20 open Pin 2 of DB-9 socket P1A not connected, no...

  • Page 103: Power Supply To External Devices Via Socket P1A

    P1A. This power supply option especially supports connectivity to analog and digital modems. Such modem devices enable global communication of the phyCORE-LPC2292/94 over the Internet or a direct dial connection. The following figure shows the location of these components on the...
  • Page 104 JP24 2 + 3 Electronically protected 5 V at pin 6 for supply of external devices connected to P1A Table 53: JP24 Power Supply to External Devices Connected to P1A on the Carrier Board © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 105: Second Serial Interface At Socket P1B

    Socket P1B is the upper socket of the double DB-9 connector at P1 P1B is connected via jumpers to the second serial interface of the phyCORE-LPC2292/94. The following description is based on a module configuration that utilizes the on-board RS-232 transceivers for the second serial interface (refer to section 3.1).
  • Page 106 RxD1_ext. signal from phyCORE-LPC2292/94 Table 55: Improper Jumper Settings for DB-9 Socket P1B (Second RS-232) If an RS-232 cable is connected to P1B by mistake, the voltage level on the RS-232 lines could destroy the phyCORE-LPC2292/94. © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 107: First Can Interface At Plug P2A

    The phyCORE-LPC2292/94 on the phyCORE Carrier Board 16.3.7 First CAN Interface at Plug P2A Plug P2A is the lower plug of the double DB-9 connector at P2. P2A is connected to the first CAN interface (CAN1) of the phyCORE-LPC2292/94 via jumpers. Depending on the configuration...
  • Page 108 Figure 25: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Carrier Board) Please make sure the CAN transceiver on the phyCORE-LPC2292/94 is not populated and Jumpers J602 and J604 are closed (refer to section 3.14 for details). © PHYTEC Meßtechnik GmbH 2006...
  • Page 109 The phyCORE-LPC2292/94 on the phyCORE Carrier Board Caution: When using the DB-9 connector P2A as CAN interface and the CAN transceiver on the Carrier Board the following jumper settings are not functional and could damage the module: Jumper Setting Description...
  • Page 110 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Carrier Board with Galvanic Separation Please make sure the CAN transceiver on the phyCORE-LPC2292/94 is not populated and Jumpers J602 and J604 are closed (refer to section 3.14 for details).
  • Page 111 The phyCORE-LPC2292/94 on the phyCORE Carrier Board CAN Bus Voltage Supply Reduction via JP39: Depending on the voltage level that is supplied over the CAN bus at P2A or P2B (VCAN_IN1+) JP39 must be configured in order to routed the applicable voltage to the CAN voltage regulator at U8 on...

  • Page 112: On Carrier Board With Galvanic Separation)

    Pin 7 of DB-9 plug P2A connected with TD1 of the phyCORE-LPC2292/94 JP11 1 + 2 Input at opto-coupler U4 on the Carrier Board is connected to SCLK0 of the phyCORE-LPC2292/94 2 + 3 Input at opto-coupler U4 on the Carrier Board is connected to A22 of the phyCORE-LPC2292/94 open...

  • Page 113: Second Can Interface At Plug P2B

    Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1. CAN transceiver populating the phyCORE-LPC2292/94 and the CAN signals from the module extend directly to plug P2B. Jumper...
  • Page 114 Figure 28: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Carrier Board) Please make sure the CAN transceiver on the phyCORE-LPC2292/94 is not populated and Jumpers J603 and J605 are closed (refer to section 3.14 for details). © PHYTEC Meßtechnik GmbH 2006...
  • Page 115 The phyCORE-LPC2292/94 on the phyCORE Carrier Board Caution: When using the DB-9 connector P2B as second CAN interface and the CAN transceiver on the Carrier Board the following jumper settings are not functional and could damage the module: Jumper Setting...
  • Page 116 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board with Galvanic Separation Please make sure the CAN transceiver on the phyCORE-LPC2292/94 is not populated and Jumpers J603 and J605 are closed (refer to section 3.14 for details).
  • Page 117 The phyCORE-LPC2292/94 on the phyCORE Carrier Board Pin 9: VCAN+ Pin 3: VCAN- Pin 7: CAN-H1 (galvanically separated) Pin 2: CAN-L1 (galvanically separated) Pin 6: VCAN- Figure 29: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Carrier Board with Galvanic Separation) ©...

  • Page 118: On Carrier Board With Galvanic Separation)

    Pin 7 at P2B is connected with CAN_H2/TD2 from the phyCORE-LPC2292/94 JP14 1 + 2 Input at opto-coupler U6 on the Carrier Board is connected to P1.21 of the phyCORE-LPC2292/94 2 + 3 Input at opto-coupler U6 on the Carrier Board is connected to A23 of the phyCORE-LPC2292/94 open...

  • Page 119: Programmable Led D3

    The phyCORE Carrier Board HD200 offers a programmable LED at D3 for user implementations. This LED can be connected to port pin P0.8 (TxD1) of the phyCORE-LPC2292/94 which is available via signal GPIO0 (JP17 = closed). A low-level at port pin P0.8 causes the LED to illuminate, LED D3 remains off when writing a high-level to P0.8.

  • Page 120: Pin Assignment Summary Of The Phycore, The Expansion Bus And The Patch Field

    16.1, signals from phyCORE-LPC2292/94 extend in a strict 1:1 assignment to the Expansion Bus connector X2 on the Carrier Board. These signals, in turn, are routed in a similar manner to the patch field on an optional expansion board that mounts to the Carrier Board at X2.
  • Page 121 The phyCORE-LPC2292/94 on the phyCORE Carrier Board However, the numbering scheme for Expansion Bus connector and patch field matrices differs from that of the phyCORE-connector, as shown in the following two figures: Figure 30: Pin Assignment Scheme of the Expansion Bus...
  • Page 122 The pin assignment on the phyCORE-LPC2292/94, in conjunction with the Expansion Bus (X2) on the Carrier Board and the patch field on an expansion board, is as follows: Signal phyCORE Module Expansion Bus Patch Field Table 69: Pin Assignment Data Bus for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board ©...
  • Page 123 The phyCORE-LPC2292/94 on the phyCORE Carrier Board Signal phyCORE Module Expansion Bus Patch Field Table 70: Pin Assignment Address Bus for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 124 Module Expansion Bus Patch Field /CS0 /CS1 /CS2 /CS3 /BLS0 /BLS1 /BLS2 /BLS3 /RESIN /RESET BOOT /PWROFF /INT_RTC Table 71: Pin Assignment Address/Control Bust for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board © PHYTEC Meßtechnik GmbH 2006 L-658e_5...
  • Page 125 Pin Assignment Port P0 for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board Check configuration of Jumper J200 on the phyCORE-LPC2292/94, refer to section 3.1. Check configuration of Jumper J202 on the phyCORE-LPC2292/94, refer to section 3.1. © PHYTEC Messtechnik GmbH 2006...
  • Page 126 P1.22 (PIPESTAT1) P1.23 (PIPESTAT2) P1.24 (TRACECLK) P1.25 (EXTIN0) P1.26 (RTCK) P1.27 (TDO) P1.28 (TDI) P1.29 (TCK) P1.30 (TMS) P1.31 (/TRST) Table 73: Pin Assignment Port P1 for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board © PHYTEC Meßtechnik GmbH 2006 L-658e_5...
  • Page 127 Pin Assignment Interface Signals for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board Check configuration of Jumper J200 on the phyCORE-LPC2292/94, refer to section 3.1. Check configuration of Jumper J202 on the phyCORE-LPC2292/94, refer to section 3.1. © PHYTEC Messtechnik GmbH 2006...
  • Page 128 39D, 42D, 47D, 41D, 42D, 43D, 52D, 57D, 62D, 46D, 47D, 48D, 67D, 72D, 77D 51D, 52D, 53D, 1E, 2E, 1F Table 75: Pin Assignment Power Supply for the phyCORE-LPC2292/94 / Carrier Board / Expansion Board © PHYTEC Meßtechnik GmbH 2006 L-658e_5...
  • Page 129 The phyCORE-LPC2292/94 on the phyCORE Carrier Board Signal phyCORE Module Expansion Bus Patch Field 50A, 51A, 53A, 18A, 19A, 20A, 4D, 5D, 7D 54A, 55A, 56A, 21A, 22A, 23A 58A, 59A, 60A, 24A, 25A, 26A, 61A, 63A, 64A, 27A, 45A, 46A,...

  • Page 130: Battery Connector Bat1

    VBAT during runtime of the module and therefore cause rapid battery discharge. It is the user's responsibility to ensure sufficient SRAM power supply during runtime. The optional battery required for the RTC buffering (refer to section 10) is available through PHYTEC (order code BL-011). 16.3.13 DS2401 Silicon Serial Number...

  • Page 131: Pin Header Connector X4

    The phyCORE-LPC2292/94 on the phyCORE Carrier Board NUMPORT Port P0.9 connected JP19 Figure 32: Connecting the DS2401 Silicon Serial Number Figure 33: Pin Assignment of the DS2401 Silicon Serial Number 16.3.14 Pin Header Connector X4 The pin header X4 on the Carrier Board enables connection of an optional modem power supply.
  • Page 132 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 133: Ethernet Port

    Ethernet Port Ethernet Port The phyCORE Carrier Board HD200 provides a 10-pin header connector at X7 for mounting the PHYTEC Ethernet transformer module. The optional add-on module is available through PHYTEC (order code EAD-003). This allows for direct connection of the...

  • Page 134: Connector X7

    GPIO37-GPIO40 to different connectors; the Ethernet interface X7 or the Expansion Bus X2. The standard configuration of the phyCORE-LPC2292/94 provides Ethernet signals on these pins. As a result the default configuration of Jumpers J1-J4 will route the signals to Ethernet interface connector X7. Changing this jumper default configuration allows use of the signals on the Expansion Bus in combination with a phyCORE module lacking the Ethernet controller.

  • Page 135: Revision History

    New images for PCB revision 1231.1 and PCM-997-V3 PCM-997-V3 PCB revision 1179.6. PCB# 1179.6 New solder jumpers for Ethernet interface configuration in section 17 added. New PCM-997-V3 PCB revision 1179.6 supports 100 Mbit/s Ethernet transmission. © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 136 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 137: Component Placement Diagram

    R203 R208 CB723 R204 R500 J617 R205 J605 Q200 R201 R206 R601 J204 CB733 R207 CB605 R200 C501 C206 XT500 C207 C500 XT200 X701 J207 C204 C205 Figure 36: phyCORE-LPC2292/94 Component Placement, Top View © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 138 RN503 U501 CB615 J620 RN504 J619 U500 R621 RN500 R506 R502 X700 X700 R505 CB616 RN600 R503 R504 U203 U604 RN700 R213 C211 C212 R211 R212 R700 Figure 37: phyCORE-LPC2292/94 Component Placement, Bottom View © PHYTEC Meßtechnik GmbH 2006 L-658e_5...

  • Page 139: Index

    Functional Components on the COM Port........55 phyCORE Carrier Board..84 Concept of the Carrier Board..77 Connector X4......119 CPLD ........28, 29 Humidity ........74 Debug Interface......65 C Interface ......40 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 140 J607........... 39 J608........... 40 P018 .......... 33 J609........... 40 P021 .......... 44 J610........... 40 Patch Field ......108 J611........... 40 PCA82C251......56 J612........... 40 phyCORE-connector .... 9, 12 J613........... 40 Physical Dimensions....73 J614........... 40 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...
  • Page 141 SMT Connector ......9 Watchdog ........39 Socket P1A (First RS-232) ..89 WDI........... 44 Socket P1B (Second RS-232)... 93 Weight........74 SPI..........43 SPI Interface ....... 40, 57 SPI Master......... 43 X701.......... 65 SPI Slave........43 © PHYTEC Messtechnik GmbH 2006 L-658e_5...
  • Page 142 © PHYTEC Meßtechnik GmbH 2006 L-658e_5...
  • Page 143 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC MeßtechnikGmbH 2006 L-658e_5...
  • Page 144 Published by © PHYTEC Meßtechnik GmbH 2006 Ordering No. L-658e_5 Printed in Germany...

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