1. Manuals
  2. Brands
  3. Phytec Manuals
  4. Motherboard
  5. phyCORE-ADuC812
  6. Hardware manual

Phytec phyCORE-ADuC812 Hardware Manual

Hide thumbs Also See for phyCORE-ADuC812:
Table of Contents

Advertisement

Quick Links

Download this manual
phyCORE-ADuC812
Hardware Manual
Edition February 2003
A product of a PHYTEC Technology Holding company

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the phyCORE-ADuC812 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Phytec phyCORE-ADuC812

Summary of Contents for Phytec phyCORE-ADuC812

  • Page 1 Hardware Manual Edition February 2003 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Meßtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Meßtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Table of Contents Preface ......................1 Introduction ..................3 1.1 Block Diagram................6 1.2 View of the phyCORE-ADuC812 ..........7 Pin Description..................9 Jumpers ....................17 3.1 J2 Supply Voltage SRAMs ............20 3.2 J1, J9, J11 SRAM Memory Capacity.........20 3.3 J3, J4, J12 Serial Interface ............21 3.4 J5 Interrupt Output of the CAN Controller .......22...
  • Page 4 A/D Converter and D/A Converter ..........57 Technical Specifications..............59 Hints for Handling the Module ............61 The phyCORE-ADuC812 on the phyCORE Development Board LD 5V..................63 15.1 Concept of the phyCORE Development Board LD 5V ..... 63 15.2 Development Board LD 5V Connectors and Jumpers ....65 15.2.1 Connectors..............
  • Page 5 Table of Contents Index of Figures and Tables Figure 1: Block Diagram phyCORE-ADuC812 ..........6 Figure 2: View of the phyCORE-ADuC812 (Top View) ......7 Figure 3: View of the phyCORE-ADuC812 (Bottom View).......8 Figure 4: Pinout of the phyCORE-Connector (Component Side)....9 Figure 5: Numbered Matrix Overview of the phyCORE-Connector (Viewed from Above)..............11...
  • Page 6 Figure 25: Pin Assignment of the DB-9 Socket P1B (Front View)..... 74 Figure 26: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on phyCORE-ADuC812, Front View) ..........76 Figure 27: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board)....... 78...
  • Page 7 Table 32: Improper Jumper Settings for Configuration of P1B ....75 Table 33: Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the phyCORE-ADuC812 ........76 Table 34: Improper Jumper Settings for the CAN Plug P2A (CAN Transceiver on phyCORE-ADuC812) ......77 Table 35: Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Development Board ........78...
  • Page 8 Table 47: Pin Assignment Analog Signal Row on the phyCORE-ADuC824 / Development Board / Expansion Board ................ 90 Table 48: Unused Pins on the phyCORE-ADuC812 / Development Board / Expansion Board ........90 Table 49: Pin Assignment Power Supply for the phyCORE-ADuC812 / Development Board / Expansion Board ................

  • Page 9: Preface

    Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments. Note: PHYTEC products lacking protective enclosures are subject to dam- age by Electro Static Discharge (ESD) and, hence, may only be unpacked, handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers.
  • Page 10 Magnetic Directives. Only after doing so the devices are allowed to be put into circulation. The phyCORE-ADuC812 is one of a series of PHYTEC Single Board Computers (SBCs) that can be fitted with different controllers and, hence, offers various functions and configurations. PHYTEC supports...

  • Page 11: Introduction

    The phyCORE-ADuC812 is a universal microcontroller board in subminiature dimensions (55 mm x 60 mm). It can be populated with ADuC812 and ADuC824 microcontrollers from Analog Device. The...
  • Page 12 Since all controlers signals and in- and outputs extend to 2.54 mm pin header rows on the edge of the board, the phyCORE-ADuC812 can be inserted like a big chip into your target application. Precise specifications for the controller populating the board can be found in the applicable controller User’s Manual or Data Sheet.
  • Page 13 Introduction The phyCORE-ADuC812 offers the following features: • subminiature Single Board Computer (55 mm x 60 mm) achieved through advanced SMD technology • Analog Device microcontrollers with 8 kByte of on-chip Flash for Code and 640 Bytes of EEPROM Flash for data •...

  • Page 14: Block Diagram

    Supervisor Supervisor (U12) (U6) (U7) (U11) 1 phyCORE specific 2 This feature is under development and is not available yet. Figure 1: Block Diagram phyCORE-ADuC812 This feature is under development and not available yet. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 15: View Of The Phycore-Aduc812

    Introduction 1.2 View of the phyCORE-ADuC812 Figure 2: View of the phyCORE-ADuC812 (Top View) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 16: Figure 3: View Of The Phycore-Aduc812 (Bottom View)

    Figure 3: View of the phyCORE-ADuC812 (Bottom View) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 17: Pin Description

    VBAT BOOT /RES /RES A16A8 A17A9 A19A11 A18A10 A20A12 A21A13 A22A14 A23A15 CANTxD CANRxD TxD0 CANL RxD0 CANH OUT0 OUT2 OUT1 OUT4 OUT3 OUT6 OUT7 OUT5 Figure 4: Pinout of the phyCORE-Connector (Component Side) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 18 Lettering of the pin connector rows progresses alphabetically from left to right (refer to Figure 5). The numbered matrix can be aligned with the phyCORE-ADuC812 (viewed from above; phyCORE-connector header pins pointing down) or with the socket of the phyCORE Development Board LD 5V / target circuitry.

  • Page 19: Figure 5: Numbered Matrix Overview Of The Phycore-Connector

    Pin Description The following figure (see Figure 5) illustrates the numbered matrix system. It shows a phyCORE-ADuC812 mounted on a phyCORE Development Board LD 5V. The shaded area of the phyCORE- connectors shown below indicates the remaining pins not used in...
  • Page 20 Address latch enable output of µC Address line of µC or of the address latch 6B, 9B, A1, A16A8, 11B,16B A21A13, A17 Address/data line of µC /EA pin of µC Table 1: Pinout phyCORE-Connector A/B (ADuC812, ADuC824) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 21 CANRxD input of the SJA1000 CANL CANL signal of the CAN transceiver CANH CANH signal of the CAN transceiver Clock output I2C bus 17D, 18D, OUT1, OUT3, Digital output port OUT5 Table 2: Pinout phyCORE-Connector C/D (ADuC812, ADuC824) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 22 RS-485 transceiver TxD0 Transmitter output of the RS-232 transceiver RxD0 Receiver input of the RS-232 transceiver 16F, 17F, OUT0, OUT2 Digital output port 18F, 19F OUT4, OUT7 Table 3: Pinout phyCORE-Connector E/F (ADuC812, ADuC824) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 23 Control input for Timer 2 IEXC2 Input capacitor C2 VREF- Reference voltage input (-) ADC4 A/D converter inputs 3H, 8H, 12H AGND Analog Ground 0 V Not used Table 5: Pinout phyCORE-Connector G/H (ADuC824) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 24 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 25: Jumpers

    Jumper 3 Jumpers For configuration purposes, the phyCORE-ADuC812 has 14 solder jumpers, some of which have been installed prior to delivery. Figure 6 illustrates the numbering of the jumper pads, while Figure 7 and Figure 8 indicate the location of the jumpers on the board z.B.: J2...

  • Page 26: Figure 8: Location Of The Jumpers (Bottom View)

    Figure 8: Location of the Jumpers (Bottom View) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 27 27 controller J14 (closed) PSCL line of the I²C (open) PSCL line of the I²C bus connected with bus disconnected from controller pin 26 controller Table 6: Jumper Description © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 28: J2 Supply Voltage Srams

    U5 = 512 kByte 2 + 3 2 + 3 U4 = 128 kByte 1 + 2* U4 = 512 kByte 2 + 3 *= Default setting, standard phyCORE-ADuC812 Table 8: J1, J9, J11 SRAM Capacity Configuration © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 29: J3, J4, J12 Serial Interface

    T1 controller signal or the OUT0 signal from the I/O port. Use of FlashTools – PHYTEC’s proprietary firmware allowing convenient on-board Flash programming – requires configuration of an RS-232 interface fopr communication purposes. Jumpers J4 and J5 must be closed at position 1+2 in this case.

  • Page 30: J5 Interrupt Output Of The Can Controller

    The following configurations are possible: Code Fetch J6 (1 kΩ) external code memory 1 + 2* internal code memory 2 + 3 *= Default setting Table 11: J6 Access to External or Internal Program Memory © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 31: J7 Interrupt Output Of The Rtc

    3.7 J8 CAN Interface An optional SJA1000 stand-alone CAN controller can populate the phyCORE-ADuC812 at U3. The signals CANTx and CANRx generated by the CAN controller are available at pins X1D12 and X1D13 of the phyCORE-connector. If the optional CAN controller is installed, a Philips PCA82C251 CAN transceiver populates the phyCORE module at U8 as well.

  • Page 32: J13, J14 I²C Bus Signals Sdata/Mosi And Sclock

    3.8 J13, J14 I²C Bus Signals SDATA/MOSI and SCLOCK Two I²C interface devices - a Real-Time Clock (RTC) at U12 and an EEPROM at U11 - are available on the phyCORE-ADuC812. These devices are connected via Jumpers J13 and J14 to port pins SDATA/MOSI and SCLOCK.

  • Page 33: Memory Model

    Note: In the event that you use FlashTools – PHYTEC’s proprietary firmware allowing convenient on-board Flash programming - the ad- dress FA16 is preset at the start of your application software (refer to section 4.5, “Control Register 1”).

  • Page 34: Memory Model Following Reset

    This enables the lower 64 kByte segment of the Flash device to be mapped within the CODE memory space of the microcontroller (FA18..FA16 = 000b). The following figure shows the memory model following a reset: Figure 9: Memory Model Following Hardware Reset © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 35: Runtime Model

    The application code is started at address 0000H which sorresponds to the physical Flash address 10000H. The phyCORE-ADuC812 is populated with 128 kByte of Flash in the standard configuration. The FlashTools firmware is always located in the lower 64 kByte bank, the second 64 kByte of Flash are available to the user for downloading the application program.
  • Page 36 00FC00H to 00FFFFH in the default configuration. Using the I/O-SW bit, the address range can be changed to 007C00H to 007FFFH (see I/O-SW in the Control Register 1). The following figure show the runtime model: Figure 10: Runtime Model © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 37: Von Neumann Model

    Memory Model 4.3 Von Neumann Model The address decoder populating the phyCORE-ADuC812 supports the von Neumann memory model. In the von Neumann memory model, RAM is mapped in both CODE and DATA memory space of the microcontroller. This enables modification of machine-readable commands in the CODE memory space during program execution by means of a DATA write access.

  • Page 38: Figure 11: Von Neumann Model

    The following figure depicts the von Neumann memory model: Figure 11: Von Neumann Model © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 39: Programming Model

    Flash, the user must ensure that the FlashTools firmware is not erased. Firmware portion of the utility program for on-board Flash programming and is pre-installed in the Flash at time of delivery. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 40: Figure 12: Programming Model

    I/O area at addresses 00FC00H to 00FC06H. If the I/O area has been switched to addresses 007C00H to 007FFFH, access of the address decoder registers is possible in the range from 007C00H to 007C06H. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 41: Control Register 1

    If using FlashTools - a firmware allowing convenient on-board Flash-programming - it should be noted that the Bit FA16 will be preset at the start of user code. This is to be noted upon installation of the software copy of the register contents. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 42: Figure 13: Flash Programming Model

    3 blocks of 256 Bytes each. Within the three 256 Byte blocks the address decoder provides a pre- decoded Chip Select signal (/CS1.../CS3) that simplifies the connection of peripheral hardware to the module. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 43: Figure 14: Configuration Of The I/O Area

    This signal is not available to the user. In order to ensure proper functioning of FlashTools firmware, enabling on-board programming of the Flash memory, it is essential that the /CS-REG signal be used as described herein. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 44 RAM. Memory space in which CODE and XDATA accesses use physical different memory devices. CODE access typically uses a ROM or Flash device, whereas XDATA access uses a RAM. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 45 Flash. The function of the bits FA[18..16] depends on the hardware configuration of the module and functions, as described above, only if the phyCORE-ADuC812 is populated with a Flash device of 512 kByte capacity. © PHYTEC Meßtechnik GmbH 2003...

  • Page 46: Address Register

    Memory space in which CODE and XDATA accesses use different physical memory devices, usually CODE access uses a ROM or Flash device, whereas XDATA access uses a RAM. Reserved bits may not be changed, the reset value (0) must remain. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 47: Mask Register

    Bit 7 Bit 0 MA15 MA14 MA13 MA12 Reset Value: 0000 0000 b Table 17: Mask Register of the Address Decoder Reserved bits are not to be changed, the reset value (0) must remain © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 48 C000H-FFFFH Table 18: Example of Address Decoder Functions Reserved bits without function for address decoding (refer to description of the register) X = irrelevant (on account of a bit set in the Mask Register) © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 49: Figure 15: Example Of A Memory Model

    Following a hardware reset, the memory space is configured as Harvard memory. Only after setting the bit (VN-EN = 1), the settings in the Address and Mask Registers are valid and regarded in the address decoding. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 50: Control Register 2

    0000 0001 b Table 19: Control Register 2 of the Address Decoder BOOT: The Boot input state of the phyCORE-ADuC812 can be read from bit 0 of Control Register 2. OE1: The phyCORE-ADuC812 is populated with a TTL output latch (74AHC573 at U15). The outputs on the latch are switched to active with bit OE1.

  • Page 51: Output Register 1

    Table 21: Output Register 1 of the Address Decoder OUT0..7: The phyCORE-ADuC812 is populated with a TTL output latch (74AHC573 at U15). Following a hardware reset, the outputs OUT0...7 are tristate and the contents of the latch is indefinite. For this reason it is recommeded to write a know bit pattern to the latch (e.g.
  • Page 52 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 53: Serial Interfaces

    Serial Interfaces 5 Serial Interfaces 5.1 RS-232 Interface An RS-232 transceiver is located on the phyCORE-ADuC812 at U9. This device adjusts the signal levels of the P3.0/RxD0 and P3.1/TxD0 lines. The RS-232 interface enables connection of the module to a COM port on a host-PC.

  • Page 54: Can Interface

    5.3 CAN Interface An optional SJA1000 stand-alone CAN controller can populate the phyCORE-ADuC812 at U3. Access to the CAN controller is possible in an 128 Byte memory range within the I/O area (refer to section 4 for detailled descriptions). Jumper J5 connects the CAN interrupt with the /INT0 signal of the ADuC812 microcontroller.
  • Page 55 For larger CAN networks, an external opto-coupler should be implemented to galvanically separate the CAN bus signals and the phyCORE-ADuC812 circuitry. This requires that the CANRx line is separated from the on-board CAN transceiver by opening Jumper J8 (refer to section 3.7). The Hewlett Packard HCPL06xx or Toshiba TLP113 HCPL06xx fast opto-coupler is recommended.
  • Page 56 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 57: Flash Memory

    8 kByte on-chip Flash memory on the controller. 6.1 On-Board Flash Memory (U4) The phyCORE-ADuC812 can be populated at U4 by a single Flash device of type 29F010 with two banks of 64 kByte each or device type 29F040 with 8 banks of 64 kByte each.

  • Page 58: Figure 16: Flash Memory Banks

    Flash is not possible. For Flash programming, program execution must be transferred out of Flash (such as into von Neumann RAM). This usually equals the interruption of a "normal" program execution cycle. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 59: On-Chip Flash Memory

    Flash Memory 6.2 On-Chip Flash Memory The phyCORE-ADuC812 is populated with an Analog Devices ADuC-812/824 microcontroller featuring 8 kByte on-chip Flash memory supporting In-System-Programming (ISP). ISP enables programming of on-chip memory while the phyCORE module is implemented in a target hardware application. Removal of the module or microcontroller is hence not necessary for programming of the on-chip memory using a dedicated programming device.

  • Page 60: Serial Eeprom (U11)

    7 Serial EEPROM (U11) As a product option, a non-volatile memory with a serial (I²C bus) interface populates space U11 on the phyCORE-ADuC812. This device is intended to store configuration parameters and user data. This memory device can be in the form of an EEPROM device or an FRAM device.

  • Page 61: Real-Time Clock Rtc-8563 (U12)

    • automatic word address incrementing • programmable alarm, timer and interrupt functions If the phyCORE-ADuC812 is equipped with a battery, the Real-Time Clock runs independently of the module’s supply voltage. Programming of the Real-Time Clock is accomplished via the I...

  • Page 62: Reset Controller (U6)

    PFI. If VBAT = 3.3 V, a voltage of 1.65 V is available at PFI. If the voltage at PFI drops below 1.25 V, the signal /PFO is released. The signals WDI and /PFO are available at the phyCORE-connector pins X1D5 and X1F5. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 63: Remote Supervisor Chip (U7)

    Space U7 is intended to be populated by an RSC1308 Remote Supervisory Chip. This IC can initiate a boot sequence via a serial interface, such as RS-232 or RS-485. The RSC can start PHYTEC FlashTools without requiring a manual reset of the phyCORE module via a Boot jumper or button.

  • Page 64: Battery Buffer

    As of the printing of this manual, a lithium battery is recommended as it offers relatively high capacity at low discharge. In the event of a power failure at VCC, the SRAM memory (U5/U13) and the RTC (U12) will be buffered by a battery connected to VBAT.

  • Page 65: D Converter And D/A Converter

    Note: Lack of the analog voltage supply (AVCC = 5V, AGND = 0V) can cause major damage to the phyCORE-ADuC812. User should also ensure that no difference between the GND and AGND potential is present (refer to the appropriate microcontroller Data Sheet).
  • Page 66 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 67: Technical Specifications

    Technical Specifications 13 Technical Specifications The physical dimensionsof the phyCORE-ADuC812 are represented in Figure 17. The module’s profile (not including the pin header connectors) is approximately 11 mm thick, with a maximum component height of 3.5 mm on the back side of the PCB and approximately 6 mm on the front-side.
  • Page 68 10 ns These specifications describe the standard configuration of the phyCORE-ADuC812 as of the printing of this manual. Please note that the module storage temperature is only 0°C to +70°C if a battery buffer is used for the RAM devices.

  • Page 69: Hints For Handling The Module

    Carefully heat neighboring connections in pairs. After a few alterna- tions, components can be removed with the solder-iron tip. Alterna- tively, a hot air gun can be used to heat and loosen the bonds. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 70 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 71: The Phycore-Aduc812 On The Phycore Development Board Ld 5V

    The phyCORE-AduC812 on the phyCORE Development Board The phyCORE-ADuC812 on the phyCORE Development Board LD 5V PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules.

  • Page 72: Figure 18: Modular Development And Expansion Board Concept With The Phycore-Aduc812

    • As the physical layout of the expansion bus is standardized across all applicable PHYTEC Development Boards, PHYTEC is able to offer various expansion boards (5) that attach to the Development Board at the expansion bus connectors. These modular expansion...

  • Page 73: Development Board Ld 5V Connectors And Jumpers

    The phyCORE-AduC812 on the phyCORE Development Board 15.2 Development Board LD 5V Connectors and Jumpers 15.2.1 Connectors As shown in Figure 19, the following connectors are available on the phyCORE Development Board LD 5V: low-voltage socket for power supply connectivity...

  • Page 74: Jumpers On The Phycore Development

    15.2.2 Jumpers on the phyCORE Development Board LD 5V Peripheral components of the phyCORE Development Board LD 5V can be connected to the signals of the phyCORE-ADuC812 by setting the applicable jumpers. The Development Board’s peripheral components are configured for use with the phyCORE-ADuC812 by means of insertable jumpers.

  • Page 75: Figure 21: Location Of The Jumpers (View Of The Component Side)

    Figure 22 shows the factory default jumper settings for operation of the phyCORE Development Board LD 5V with the standard phyCORE-ADuC812 (standard = ADuC812 controller, use of the RS-232 interface, the optional RS-485 interface, the first CAN interface, LED D3, the Boot button on the Development Board).

  • Page 76: Board Ld 5V

    The phyCORE Development Board LD 5V supports two main supply voltages for the start-up of various phyCORE modules. When using the phyCORE-ADuC812, only one main supply voltage is required, VCC1 with 5V. The connector pins for a second supply voltage on the phyCORE-ADuC812 are not defined.

  • Page 77: Functional Components On The Phycore Development Board Ld 5V

    5 V as analog supply voltage AVCC to the phyCORE-ADuC812 Table 24: JP9, JP36 Configuration of the Supply Voltages VCCI and AVCC If the phyCORE-ADuC812 is purchased in a Rapid Development Kit, an appropriate 5 V power adapter is included. © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 78: Figure 23: Connecting The Supply Voltage At X1

    JP9, JP36 Improper Jumper Settings for the Supply Voltages Setting Jumper JP9 to position 1+2 configures a main power supply to the phyCORE-ADuC812 of 3.3 V which could destroy the module. If Jumper JP9 is open, no main power supply is connected to the phyCORE-ADuC812.

  • Page 79: Starting Flashtools

    Starting FlashTools requires Jumper J1 on the phyCORE-ADuC812 closed at positions 1+2! Refer to section 3.5 for details. In order to start FlashTools on the phyCORE-ADuC812, the Boot pin (X1D6) of the phyCORE module must be connected to a high-level signal at the time the Reset signal changes from its active to the inactive state.
  • Page 80 2. The Boot input of the phyCORE-ADuC812 can also be perma- nently connected to VCC. This spares pushing the Boot button during a hardware reset or power-on. Jumper Setting Description JP28 2 + 4 Boot input connected permanently with VCC.

  • Page 81: First Serial Interface At Socket P1A

    Socket P1A is the lower socket of the double DB-9 connector at P1. P1A is connected via jumpers to the first serial interface of the phyCORE-ADuC812. When connected host-PC, phyCORE-ADuC812 can be rendered in FlashTools mode via signals applied to the socket P1A (refer to section 15.3.2). Jumper Setting Description JP20...

  • Page 82: Socket P1B

    15.3.4 Socket P1B Socket P1B is the upper socket of the double DB-9 connector at P1. The phyCORE-ADuC812 does not support a second RS-232 interface. Socket P1B remains unused. Jumper Setting Description open Pin 2 of the DB-9 socket P1B not connected...
  • Page 83 The phyCORE-AduC812 on the phyCORE Development Board Caution: When using the phyCORE-ADuC812 mounted on a phyCORE Development Board LD 5V the following jumper settings are not functional and could damage the module: Jumper Setting Description closed Pin 2 of the DB-9 socket P1B is connected to...

  • Page 84: Can Interface At Plug P2A

    Plug P2A is the lower plug of the double DB-9 connector at P2. P2A connected optional interface phyCORE-ADuC812 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1. CAN transceiver populating the phyCORE-ADuC812 is enabled and the CAN signals from the module extend directly to plug P2A.
  • Page 85 The phyCORE-AduC812 on the phyCORE Development Board Caution: When using the DB-9 plug P2A as CAN interface and the CAN transceiver on the phyCORE-ADuC812 the following jumper settings are not functional and could damage the module: Jumper Setting Description JP31...

  • Page 86: Figure 27: Pin Assignment Of The Db-9 Plug P2A (Can Transceiver On Development Board)

    2. The CAN transceiver populating the phyCORE-ADuC812 is disabled; CAN signals generated by the CAN transceiver (U2) on the Development Board extending to connector P2A without galvanic seperation: Jumper Setting Description JP31 1 + 2 Pin 2 of DB-9 plug P2A connected with CAN-L0 from...
  • Page 87 The phyCORE-AduC812 on the phyCORE Development Board Caution: When using the DB-9 connector P2A as CAN interface and the CAN transceiver on the Development Board, the following jumper settings are not functional and could damage the module: Jumper Setting Description...
  • Page 88 3. The CAN transceiver populating the phyCORE-ADuC812 is disabled; CAN signals generated by the CAN transceiver (U2) on the Development Board extend to connector P2A with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 13 V, 14 to 20 V or 21 to 27 V. The external power supply must be only connected to either P2A or P2B.
  • Page 89 The phyCORE-AduC812 on the phyCORE Development Board Pin 9: VCAN+ Pin 3: VCAN- Pin 7: CAN-H0 (galvanically separated) Pin 2: CAN-L0 (galvanically separated) Pin 6: VCAN- Figure 28: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board with Galvanic Separation)

  • Page 90: Interface At Plug P2B

    RS-485 interface signals phyCORE-ADuC812 via jumpers. The RS-485 interface is an alternative function of the serial interface signals on the ADuC812 controller. The default configuration of the phyCORE-ADuC812 activates the RS-232 interface. In order to enable the RS-485 signals, different jumper settings on the phyCORE-ADuC812 are required (refer to section 3.3 for details).
  • Page 91 The phyCORE-AduC812 on the phyCORE Development Board Caution: When using the DB-9 plug P2B as RS-485 interface the following jumper settings are not functional and could damage the module: Jumper Setting Description JP33 2 + 3 Pin 2 of DB-9 plug P2B connected with CAN-L1 signal...

  • Page 92: Programmable Led D3

    LED at D3 for user implementations. This LED can be connected to a port pin at GPIO0 (JP17 = 1+2) or the data bus via a latch U14 (JP17 = 2+3). When using the phyCORE-ADuC812, the factory default configuration enables control of LED D3 using port pin P3.4 (GPIO0).

  • Page 93: Pin Assignment Summary Of The Phycore, The Expansion Bus And The Patch Field

    15.1, signals from phyCORE-ADuC812 extend in a strict 1:1 assignment to the expansion bus connector X2 on the Development Board. These signals, in turn, are routed in a similar manner to the patch field on an optional expansion board that mounts to the Development Board at...

  • Page 94: Figure 30: Pin Assignment Scheme Of The Expansion Bus

    Figure 30: Pin Assignment Scheme of the Expansion Bus A B C D E F Figure 31: Pin Assignment Scheme of the Patch Field © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 95 The phyCORE-AduC812 on the phyCORE Development Board The pin assignment on the phyCORE-ADuC812, in conjunction with the expansion bus (X2) on the Development Board and the patch field on an expansion board, is as follows: Signal phyCORE-ADuC812 Expansion Bus Patch Field P0.0/ AD0...
  • Page 96 Expansion Bus Patch Field ClkIn ClKOut P3.2 / INT0 P3.3/ /INT1 /CS1 /CS2 /CS3 Table 43: Pin Assignment Control Signals for the phyCORE-ADuC812 / Development Board / Expansion Board Signal phyCORE-ADuC812 Expansion Bus Patch Field BOOT /RESET /RESIN /RESOUT T0 (P3.4) T1 (P3.5)
  • Page 97 Patch Field OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Table 45: Pin Assignment Input and Output Port for the phyCORE-ADuC812 / Development Board / Expansion Board Signal phyCORE-ADuC812 Expansion Bus Patch Field VREF 4H, 7G 52D, 55D 17F, 18D...
  • Page 98 20B to 32B Board not being 20C to 32C used by the 20D to 32C phyCORE- 20E to 32E ADuC812 20F to 32F Table 48: Unused Pins on the phyCORE-ADuC812 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 99 3D, 9D, 14D, 43D, 46D, 47D, 19D, 24D, 29D, 48D, 51D, 52D, 34D, 39D, 44D, 49D, 54D, 59D, 64D, 69D, 74D, Table 49: Pin Assignment Power Supply for the phyCORE-ADuC812 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 100: Battery Connector Bat1

    The mounting space BAT1 (see PCB stencil) is provided for connection of a battery that buffers volatile memory devices (SRAM) and the RTC on the phyCORE-ADuC812. The Reset controller on the phyCORE-ADuC812 is responsible for switching from a normal power supply to a back-up battery. This optional battery required for this function (refer to section 11) is available through PHYTEC (order code BL-003).

  • Page 101: Pin Header Connector X4

    The phyCORE-AduC812 on the phyCORE Development Board NUMPORT U14/U15 connected JP19 Port P3.5 Figure 32: Connecting the DS2401 Silicon Serial Number Figure 33: Pin Assignment of the DS2401 Silicon Serial Number 15.3.11 Pin Header Connector X4 The pin header X4 on the Development Board enables connection of an optional modem power supply.

  • Page 102: Revision History

    14-Feb-2003 Manual L-461e_3 Drawing for figure 14 corrected, /CSCAN range was wrong. PCM-012 Error in table 43 (pins 2C and 3A are N.C.) corrected. PCB# 3089.1 This revision history table added. PCM-992 PCB# 1184.1 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...

  • Page 103: Index

    Control Register 1 .....37 J11 ..........20 Control Register 2 .....46 J12 ..........22 J13 ..........27 D/A Converter ......63 J14 ..........27 Default Memory Model.....29 J2 ..........20 Development Board J3 ..........22 Connectors and Jumpers ..72 J4 ..........22 DS2401........100 J5 ..........23 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 104 Power Supply ......76 U7..........61 PRG-EN ........37 U9........22, 49 Programming Model ....35 VBAT........62 Real-Time Clock ....... 58 VN-EN ........40 Remote Supervisor Chip ... 61 Von Neumann Model ....33 Reset button ......73 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 105 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Meßtechnik GmbH 2003 L-461e_3...
  • Page 106 Published by © PHYTEC Meßtechnik GmbH 2003 Ordering No. L-461e_3 Printed in Germany...

Table of Contents