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Phytec phyCORE-LPC2292/94 Manuals
Manuals and User Guides for Phytec phyCORE-LPC2292/94. We have
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Phytec phyCORE-LPC2292/94 manual available for free PDF download: Hardware Manual
Phytec phyCORE-LPC2292/94 Hardware Manual (144 pages)
Brand:
Phytec
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Table of Contents
3
Preface
13
1 Introduction
15
Block Diagram
18
Figure 1: Block Diagram Phycore-LPC2292/94
18
View of the Phycore-LPC2292/94
19
Figure 2: Top View of the Phycore-LPC2292/94
19
Top View
19
Bottom View
20
Figure 3: Bottom View of the Phycore-LPC2292
20
2 Pin Description
21
Figure 4: Pinout of the Phycore-Connector (Top View, with Cross Section Insert)
23
Table 1: Pinout of the Phycore-Connector X1
28
3 Jumpers
29
Figure 5: Numbering of the Jumper Pads
29
Figure 6: Location of the Jumpers (Top View)
29
Figure 7: Location of the Jumpers (Bottom View)
30
J200, J202 Second Serial Interface
36
Table 2: Jumper Settings
36
J201, J203 First Serial Interface
37
Table 3: J200, J202 Second Serial Interface Configuration
37
Table 4: J201, J203 First Serial Interface Configuration
37
J204 A/D Converter
38
J205, J206 Chip Select Configuration
38
Table 5: J204 A/D Converter Reference Voltage
38
J207 MCKO Signal
39
Table 6: J205, J206 Chip Select Configuration
39
Table 7: J207 MCKO Signal Configuration
39
J208, J209 Flash Size Configuration
40
Table 8: J208, J209 Flash Memory Size Configuration
40
J210, J211 RAM Size Configuration
41
Table 9: J210, J211 RAM Memory Size Configuration
41
J300 Flash Ready/Busy Configuration
42
Table 10: J300 Flash Ready/Busy Configuration
42
J301, J302 Flash Write Protection Configuration
43
Table 11: J301, J302 Flash Write Protection Configuration
43
J400, J401 SRAM Configuration
44
J402 SRAM Supply Voltage
44
Table 12: J400, J401 SRAM Access Configuration
44
Table 13 J402 SRAM Supply Voltage Configuration
44
J500 through J509 Ethernet Controller SMSC Lan91C111Configuration
45
Table 14: J503 Ethernet Chip Select Signal Configuration
45
Table 15: J501 Ethernet Interrupt Signal Configuration
45
Table 16: J503 Ethernet Ready Signal Configuration
46
Table 17: J504 Ethernet LAN_IRQ Pull-Up Configuration
46
Table 18: J505, J506, J507 Ethernet EEPROM Configuration
46
Table 19: J508 Ethernet EEPROM Enable Configuration
47
Table 20: J509 Ethernet Nlnk Pin Configuration
47
J600, J601, J616 CAN Transceiver Configuration
48
Table 21: J600, J601 CAN Transceiver Activation
48
J602, J603, J604, J605 CAN Interfaces
49
Table 22: J616 CAN Transceiver Supply Configuration
49
J606 Write Protection of SPI EEPROM
50
Table 23: J602, J603, J604 and J605 CAN Interface Configuration
50
Table 24: J606 EEPROM Write Protection
50
J607 Watchdog Configuration
51
Table 25: J607 Watchdog Configuration
51
J608, J609, J610 I C Interface
52
J611, J612, J613, J614 SPI0 Interface
52
Table 26: J608, J609, J610 I C Interface Configuration
52
Table 27: J611, J612, J613, J614 SPI Interface Signal Configuration
52
J615 CAN Bus Level Configuration
53
Table 28: J615 CAN Level Configuration
53
J616, J617 CAN Transceiver VCC, Pin 5
54
Table 29: J616, J617 CAN Transceiver VCC at Pin #5
54
J618 VDD_V3V3 Supply Control
55
J619, J620 SPI Master/Slave Selection
55
Table 30: J618 VDD_V3V3 Supply Control
55
Table 31: J619, J620 SPI Master/Slave Selection
55
J621 WDI Signal Source
56
J622 RESET Signal Source
56
Table 32: J621 WDI Signal Source
56
J800, J801 ETM/OCDS Connector Configuration (Only with Debugcore-LPC2292/94)
57
Table 33: J622 RESET Signal Source
57
C210 CLKIN Configuration
58
4 System Configuration
59
System Startup Configuration
59
Starting the LPC2292/94 ISP Mode
60
5 Memory Models
61
Figure 8: Phycore-LPC2292/94 Memory Model
63
6 Serial Interfaces
67
Interfaces
67
CAN Interface
68
7 Serial EEPROM (U607)
69
8 On-Board Flash Memory (U300-U303)
70
9 LAN91C111 Ethernet Controller (U501)
71
Figure 9: Ethernet Connection to LPC2292/94 Controller
71
MAC Address
72
Ethernet EEPROM (U500)
73
10/100Base-T Interface
73
10 Real-Time Clock RTC-8564 (U604)
74
11 Battery Buffer
75
12 Debug Interface X701
77
Figure 10: JTAG Interface (Top View)
77
Figure 11: JTAG Interface (Bottom View)
78
13 Debugcore-LPC2292/94
81
Figure 12: Debugcore-LPC2292/94 (Top View)
81
Figure 13: Debugcore-LPC2292/94 (Bottom View)
82
14 Technical Specifications
85
Figure 14: Physical Dimensions
85
15 Hints for Handling the Phycore-LPC2292/94
87
16 The Phycore-LPC2292/94 on the Phycore Carrier Board HD200
89
Concept of the Phycore Carrier Board HD200
89
Figure 15: Modular Development and Expansion Board Concept with the Phycore-LPC2292/94
90
Carrier Board HD200 Connectors and Jumpers
91
Connectors
91
Figure 16: Location of Connectors on the Phycore Development Board HD200
91
Jumpers on the Phycore Carrier Board HD200
93
Figure 17: Numbering of Jumper Pads
93
Figure 18: Location of the Jumpers (View of the Component Side)
93
Figure 19: Default Jumper Settings of the Phycore Development Board HD200 with Phycore-LPC2292/94
94
Unsupported Features and Improper Jumper Settings
95
Functional Components on the Phycore Carrier Board HD200
96
Power Supply at X1
96
Figure 20: Connecting the Supply Voltage at X1
97
Starting the ISP Command Handler
98
Phycroe-LPC2292/4 Boot Memory Configuration
100
First Serial Interface at Socket P1A
101
Figure 21: Pin Assignment of the DB-9 Socket P1A as First
101
Power Supply to External Devices Via Socket P1A
103
Figure 22: Location of Components at U12 and U13 for Power Supply to External Subassemblies
103
Second Serial Interface at Socket P1B
105
First CAN Interface at Plug P2A
107
On Carrier Board with Galvanic Separation)
112
Second CAN Interface at Plug P2B
113
On Carrier Board with Galvanic Separation)
118
Programmable LED D3
119
User Push Button S3
119
Pin Assignment Summary of the Phycore, the Expansion Bus and the Patch Field
120
Battery Connector BAT1
130
DS2401 Silicon Serial Number
130
Pin Header Connector X4
131
17 Ethernet Port
133
Connector X7
134
18 Revision History
135
19 Component Placement Diagram
137
Index
139
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