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Phytec phyCORE-TC1775 Hardware Manual

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TC1775
Hardware Manual
Edition July 2006
A product of a PHYTEC Technology Holding company

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  • Page 1 TC1775 Hardware Manual Edition July 2006 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Messtechnik GmbH neither gives any guar- antee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Table of Contents Preface Introduction..................3 1.1 Block Diagram ................6 1.2 View of the phyCORE-TC1775........... 7 Pin Description ..................9 Jumpers....................23 Power System and Reset Behavior ..........31 Boot Characteristics................33 System Memory................. 35 6.1 Memory Model following Reset ..........35 6.2 Runtime Memory Model............
  • Page 4 Expansion Bus and the Patch Field....... 81 14.3.10 DS2401 Silicon Serial Number........92 14.3.11 Pin Header Connectors X4 and X5....... 93 debugCORE-TC1775 on the Development Board......95 Revision History................99 A.1 Release Notes................100 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 5 Table of Contents Index of Figures Figure 1: Block Diagram phyCORE-TC1775 ........6 Figure 2: View of the phyCORE-TC1775 (Controller Side)....7 Figure 3: View of the phyCORE-TC1775 (Connector Side)....8 Figure 4: Pinout of the phyCORE-Connector (Connector Side) ..11 Figure 5: Numbering of the Jumper Pads ..........
  • Page 6 Development Board with Galvanic Separation) ....76 Figure 23: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on phyCORE-TC1775, Front View) ........77 Figure 24: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver on Development Board) ............78...
  • Page 7 Table 15: Improper Jumper Settings for DB-9 Socket P1A as Second RS-232 ................73 Table 16: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the phyCORE-TC1775 ......74 Table 17: Jumper Configuration for CAN Plug P2A Using the CAN Transceiver on the Development Board ......75...
  • Page 8 Table 23: JP29, JP30 Configuration of the Ethernet Interface....80 Table 24: JP17 Configuration of the Programmable LED D3....80 Table 25: Pin Assignment Data Bus for the phyCORE-TC1775 / Development Board / Expansion Board (Class B Pins Nominal 2.5 V, 3.3 V Tolerant) ..........83...
  • Page 9 Table of Contents Table 38: Activating the Wiggler ............... 96 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 10 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 11: Preface

    (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m. © PHYTEC Messtechnik GmbH 2006...
  • Page 12 The phyCORE-TC1775 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports all...

  • Page 13: Introduction

    Introduction 1 Introduction The phyCORE-TC1775 belongs to PHYTEC’s phyCORE Single Board Computer module family. The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a microcontroller...
  • Page 14 The phyCORE-TC1775 is a subminiature (72 x 57 mm) insert-ready Single Board Computer populated with Infineon’s TC1775 Tricore microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch (0.635 mm) connectors aligning two sides of the board, allowing it to be plugged like a “big chip”...

  • Page 15: Memory Configuration

    • Dual CAN port: 82C251CAN transceiver 82C251 for both channels; TTL level can be configured • JTAG/Debug port • Available in standard- (0...+70° C) temperature range Please contact PHYTEC for more information about additional modul configurations. © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 16: Block Diagram

    RS-232 Transceiver UART B RXD2-TTL, TXD2-TTL A_CANL, A_CANH CAN Transceiver CAN A A_CANRX, A_CANTX CAN B B_CANL, B_CANH CAN Transceiver B_CANRX, B_CANTX Ethernet ETH_RXD, ETH_TXD ETH_LinkLED, Controller ETH_LanLED JTAG Figure 1: Block Diagram phyCORE-TC1775 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 17: View Of The Phycore-Tc1775

    Introduction 1.2 View of the phyCORE-TC1775 Figure 2: View of the phyCORE-TC1775 (Controller Side) © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 18: Figure 3: View Of The Phycore-Tc1775 (Connector Side)

    Figure 3: View of the phyCORE-TC1775 (Connector Side) © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 19: Pin Description

    (SMT) connectors (0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the phyCORE-TC1775 to be plugged into any target application like a "big chip". A new numbering scheme for the pins on the phyCORE-connector has been introduced with the phyCORE specifications.
  • Page 20 Development Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner of the phyCORE-TC1775 marked with a white triangle. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

  • Page 21: Figure 4: Pinout Of The Phycore-Connector (Connector Side)

    Pin Description The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-TC1775 with SMT phyCORE- connectors on its underside. Figure 4: Pinout of the phyCORE-Connector (Connector Side) Many of the controller port pins accessible at the connectors along the edges of the board have been assigned alternate functions that can be activated via software.
  • Page 22 Microcontroller's wait signal X1A35 I/O Pin 87 of PLD U16 for general purpose /HLDA I/O Hold acknowledge I/O of the processor Microcontroller’s write signal X1A50 I/O Pin 19 of PLD U16 for general purpose © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 23 I/O I/O Port P89; solder jumper J51 must be closed at position 1+2 in order to use this function Alternative: /CSOVL ; solder jumper J51 must be closed at position 2+3 in order to use the alternative function © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 24 Byte control signal for data lines D[8..15]. /HOLD Processor’s hold request input /BREQ I/O Processor’s bus request signal Alternative: Port 4.13 X1B48 I/O Pin 86 of PLD U16 for general purpose /ADV Processor’s address valid output © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 25 I/O I/O Port P88; solder jumper J50 must be closed at position 1+2 in order to use this function Alternative: /CSEMUL ; solder jumper J51 must be closed at position 2+3 in order to use the alternative function © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 26 Alternative: port P12.5 RxD1 RxD input of the RS-232 transceiver for the 2 serial interface, J10 must be closed to use this interface TxD1 TxD output of the RS-232 transceiver for the serial interface © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 27 Alternative: I/O signal for General Purpose Timer Arrays (GPTA) IN0/OUT0 39C, 40C P1014, P1013 I/O I/O port P10 41C,43C P1011, P108 Alternative: I/O signal for General Purpose Timer Arrays (GPTA) IN46/OUT46, IN45/OUT45, IN43/OUT43, IN40/OUT40 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 28 74C, 75C AN9, AN8 Alternative: none 76C, 78C AN6, AN3 79C, 80C AN1, AN0 72C, 77C Vagnd1 Analog Ground 0V for ADC0. Vagnd0 is connected with GND via solder jumper J28 J28 = 3+4 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 29 I/O Master transmit / slave receive output / input of the first synchronous serial interface Alternative: port P13.7 MTSR0 I/O Master receive / slave transmit input / output of the first synchronous serial interface Alternative: port P13.8 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 30 ADC0 external trigger input Alternative: port P12.8 AD0EMUX2 Control input 2 for ADC0 multiplexer 60D,61D AN30, AN28 Analog inputs of the ADC1 62D, 63D AN27, AN25 Alternative: none 65D, 66D AN22, AN20 67D, 68D AN19, AN17 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 31: Table 1: Pinout Of The Phycore-Connector X1

    Ground 0 V for analog signals of the ADC0. Vagnd0 is connected with GND via solder Jumper J28 = 3+4. VAREF0 Reference voltage input for ADC0, max. +5 VDC Table 1: Pinout of the phyCORE-Connector X1 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 32 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 33: Jumpers

    Jumpers 3 Jumpers For configuration purposes, the phyCORE-TC1775 has 38 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the jumper pads, while Figure 6 and Figure 7 indicate the location of the jumpers on the module.

  • Page 34: Figure 7: Location Of The Jumpers (Connector Side) And Default Settings (Phycore-Tc1775 Standard Version)

    Figure 7: Location of the Jumpers (Connector Side) and Default Settings (phyCORE-TC1775 Standard Version) © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 35 TC1775 (RXD0) with the RS-232 transceiver at U20. open RxD0A can be used as port P12.12, no connection to RS-232 transceiver. closed RxD0A used as RS-232 input and conneted to U20. footprint 0R / SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 36 Please refer to the „System. Unit“ Manual for the TC1775 section 3.1.2.5 before changing this jumper setting. Please refer to the „System. Unit“ Manual for the TC1775 section 3.1.2.5. PLL on TC1775 is used. footprint 0R / SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 37 A2 = 0, A1 = 1, A0 = 0 (0xA4 / 0xA5) 2+3, 1+2 A2 = 1, A1 = 1, A0 = 0 (0xAC / 0xAD) C slave address 0xAC for write operations and 0xAE for read access. footprint 0R / SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 38 PLD at U16. open, open 1 MByte standard Flash devices or nn PLD at U16 closed, open 2 MByte standard Flash devices open, closed 4 MByte standard Flash devices footprint 0R / SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 39 Configures/enables the write protection feature for standard Flash devices (low level=write protection active) write protection diabled write protection could be defined with port P84 open write protection enabled (R21 must be populated) footprint 0R / SMD 0402 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 40: Table 2: Jumper Settings

    Access to U12 is generated from U16. In this case U8 must NOT be populating the module. Access to U12 is generated directly from the CPU at footprint 0R / SMD 0402 Table 2: Jumper Settings © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 41: Power System And Reset Behavior

    Power System and Reset 4 Power System and Reset Behavior Operation of the phyCORE-TC1775 requires three different supply voltages. Supply voltage 1: +2.5 V Supply voltage 2: +5 V Supply voltage 3: +3.3V Note: All three supply voltages are required for proper operation of the module.
  • Page 42 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 43: Boot Characteristics

    /BOOT = 1 (inactive) Jumper (default) CFG[0..3] Boot Source PC Start Address JP18 = 2 + 3 1011 external memory A00000000H JP19 = 1 + 2 (cached) JP20 = 2 + 3 JP21 = 2 + 3 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 44 BUSCON0. From this point on there is a valid configuration for read accesses to the external Flash memory, and the program execution can begin at address A0000000h. valid boot memory configuration word phyCORE-TC1775 is 0x8280. © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 45: System Memory

    6.1 Memory Model following Reset The internal Chip Select logic provided by the TC1775 controller is used exclusively on the phyCORE-TC1775. Hence the memory model as described in the TC1775 User's Manual is valid after reset. 6.2 Runtime Memory Model The runtime memory model is configured via software using the internal registers of the TC1775.

  • Page 46: Table 3: Runtime Memory Map

    You can find the values in the column "No. of Address Bits compared..." as hexadecimal values. These values can be put directly into bits 4-7 of the corresponding EBU_ADDSEL register. © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 47: Flash Memory

    System Memory 6.3 Flash Memory Use of Flash as non-volatile memory on the phyCORE-TC1775 provides an easily reprogrammable means of code storage. The standard Flash memory operates in 16-bit mode and has 32-bit organization on the module. The burst-mode Flash operates in 32-bit mode.

  • Page 48: Standard Flash (U14, U15)

    /CS0 when burst mode is activated. 6.3.2 Standard Flash (U14, U15) The following list shows standard Flash devices can populate the phyCORE-TC1775. Depending on the component market situation PHYTEC reserves the right to use other pin-compatible Flash devices from different manufacturers : Type Capacity...

  • Page 49: Serial Memory, Eeprom/Fram/Sram (U13)

    100.000 erase/program cycles. 6.4 Serial Memory, EEPROM/FRAM/SRAM (U13) The phyCORE-TC1775 features a non-volatile memory with an I interface. This memory can be used for storage of configuration data or operating parameters, that must not be lost in the event of a power interruption.

  • Page 50: Figure 8: I 2 C Slave Address Of The Serial Memory

    C A d d re ss o f th e S e ria l M e m o r y R /W 0 x A J 1 7 J 1 6 G N D Figure 8: C Slave Address of the Serial Memory © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 51: Table 6: I 2 C Addresses For Serial Memory

    1 + 2 Table 6: C Addresses for Serial Memory Address lines A1 and A2 are not always made available by certain serial memory types. This should be noted when configuring the I bus slave address. © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 52 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 53: Serial Interfaces

    TxD line of the COM port; while the TxD0 line is connected to the RxD line of the COM port. The Ground potential of the phyCORE-TC1775 circuitry needs to be connected to the applicable Ground pin on the COM port as well.

  • Page 54: Can Interface

    7.2 CAN Interface The phyCORE-TC1775 is designed to house two CAN transceivers at U22 and U21 (either PCA82C251 or Si9200EY). The CAN bus transceiver devices support signal conversion of the CAN transmit (CANTx) and receive (CANRx)lines. The CAN transceiver supports up to 110 nodes on a single CAN bus.

  • Page 55: On-Chip Debug Support

    (Wiggler, etc.) can be connected at X3, which allows for connectivity of the TC1775 to a host PC. The phyCORE-TriCORE Develoment Board (article number PCM-993) integrates such a converter, thus allowing direct connectivity with a development computer (refer to section 14). © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 56: Table 7: Ocds1 Connector X3 Pin Assignment

    OCDS1 Connector X3 Pin Assignment Note: Special care must be take when implementing your own external converter in order to ensure the applicable 2.5 VDC supply voltage is applied at pin 2 of connector X3. © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 57: Cs8900A Ethernet Controller

    Ethernet controller are available in the corresponding data sheet. I/O and Mode The phyCORE-TC1775 supports only the I/O mode as memory mode of the CS8900A controller. It is important to note the specific access type when creating or using software drivers. Following a reset the I/O mode is active per default.

  • Page 58: Interrupt Control

    IP number to the hardware's MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE-TC1775 is located on the bar code sticker attached to the module.

  • Page 59: Configuration Data In Eeprom (U10)

    MAC address at time of delivery (refer to section 8.5, "MAC Address"). 8.7 10Base-T Interface The phyCORE-TC1775 has been designed for use in 10Base-T networks exclusively. The AUI interface of the CS8900A is not available to the user. In order to connect the module to an existing 10Base-T network some external circuitry is required.

  • Page 60: Real-Time Clock Rtc-8564 (U24)

    • Automatic word address incrementing • Programmable alarm, timer and interrupt functions If the phyCORE-TC1775 is equipped with a battery (VBAT), the Real-Time Clock runs independently of the board’s power supply. Programming the Real-Time Clock is done via the I...

  • Page 61: Standby Power Supply

    In some applications it is desirable to disconnect all supply voltages from the module, but still maintain certain data in the volatile memory. For such cases the phyCORE-TC1775 offers the input pin VBAT (X1C6). If a voltage of 2.5 V is supplied over VBAT, then the data is...
  • Page 62 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 63: Debugcore-Tc1775

    Trace port. Since the debugCORE is 100 % function-compatible with the phyCORE-TC1775, it can easily be inserted directly into the application in place of the phyCORE-TC1775 for the purpose of hardware debugging. Please note that the debugCORE-TC1775 is slightly larger than the standard phyCORE-TC1775 module due to the additional debugging connector added to the standard circuitry.

  • Page 64: Figure 9: Positions Of The Additional Components On The

    The following figure shows the positions of the additional components and the slightly increased size. 70mm Figure 9: Positions of the Additional Components on the debugCORE-TC1775 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 65: Connecting An Emulator

    X2. Debugging on a 'deeper' level is possible with the use of these signals, since the trace information provides information about the internal processes of the CPU. The trace port is connected to the emulator in addition to the JTAG port. © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 66 Please note that when using the Trace port (OCDS2) port 5 of the controllers is no longer available for other I/O functions. © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 67: Technical Specifications

    Technical Specifications 12 Technical Specifications The physical dimensions of the phyCORE-TC1775 are represented in Figure 11. The module's profile is ca. 6 mm thick, with a maximum component height of 2.0 mm on the backside of the PCB and approximately 2.8 mm on the front side. The board itself is approximately 1.2 mm thick.
  • Page 68 Real-Time Clock supply VBAT = 2.5 V, 2.5 V voltage=off, 3.3 V voltage=off, 5 V voltage=off, 20°C TBD µA These specifications describe the standard configuration of the phyCORE-TC1775 as of the printing of this manual. © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 69 Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-TC1775. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (2 mm) on the underside of the phyCORE must be subtracted.

  • Page 70: Hints For Handling The Phycore-Tc1775

    13 Hints for Handling the phyCORE-TC1775 Removal of various components, such as the microcontroller and the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering.

  • Page 71: The Phycore-Tc1775 On The Phycore-Tricore Development Board

    The phyCORE-TC1775 on the Development Board The phyCORE-TC1775 on the phyCORE-TriCORE Development Board PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start-up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules.

  • Page 72: Figure 12: Modular Development And Expansion Board Concept With The Phycore-Tc1775

    • As the physical layout of the expansion bus is standardized across all applicable PHYTEC Development Boards, we are able to offer various expansion boards (5) that attach to the Development Board at the expansion bus connectors. These modular expansion...

  • Page 73: Phycore-Tricore Development Board Connectors And Jumpers

    The phyCORE-TC1775 on the Development Board 14.2 phyCORE-TriCORE Development Board Connectors and Jumpers 14.2.1 Connectors As shown in Figure 13, the following connectors are available on the phyCORE-TriCORE Development Board: low-voltage socket for power supply connectivity mating receptacle for expansion board connectivity...
  • Page 74 Sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 75: Jumpers On The Phycore-Tricore Development Board

    The phyCORE-TC1775 on the Development Board 14.2.2 Jumpers on the phyCORE-TriCORE Development Board Peripheral components of the phyCORE-TriCORE Development Board can be connected to the signals of the phyCORE-TC1775 by setting the applicable jumpers. The Development Board’s peripheral components are configured for use with the phyCORE-TC1775 by means of insertable jumpers.

  • Page 76: Figure 16: Default Jumper Settings Of The Phycore-Tricore Development Board With Standard Phycore-Tc1775

    Figure 16 shows the factory default jumper settings for operation of the phyCORE-TriCORE Development Board with the standard phyCORE-TC1775 (use of two RS-232 interfaces, LED D3, the Boot button etc. on the Development Board). Jumper settings for other functional configurations of the phyCORE-TC1775 module mounted on the Development Board are described in section 14.3.

  • Page 77: Functional Components On The Phycore-Tricore Development Board

    Development Board supported phyCORE-TC1775 and appropriate jumper settings to activate these components. Depending on the specific configuration of the phyCORE-TC1775 module, alternative jumper settings can be used. These jumper settings are different from the factory default settings as shown in Figure 16 and enable alternative or additional functions on the phyCORE-TriCORE Development Board depending on user needs.

  • Page 78: Activating The Bootstrap Loader

    U18. Applying a low-level signal at pin X1C9 of the phyCORE-TC1775 (via the Boot input) activates the electronic switch.

  • Page 79: Table 10: Jp22, Jp23, Jp34 Configuration Of Boot Via Rs-232

    The phyCORE-TC1775 on the Development Board 2. It is also possible to start the Bootstrap Loader via external signals applied to the DB-9 socket P1A. This requires control of the signal transition on the Reset line via pin 7 while a static low-level is applied to pin 4 for the Boot signal.

  • Page 80: First Serial Interface At Socket P1A

    Socket P1A is the lower socket of the double DB-9 connector at P1. P1A is connected via jumpers to the first serial interface of the phyCORE-TC1775. When connected host-PC, phyCORE-TC1775 can be rendered in Bootstrap mode via signals applied to the socket P1A (refer to section 14.3.2). Jumper Setting Description JP20...

  • Page 81: Table 13: Improper Jumper Settings For Db-9 Socket P1A As

    The phyCORE-TC1775 on the Development Board Caution: When using the DB-9 socket P1A as RS-232 interface on the phyCORE-TC1775 the following jumper settings are not functional and could damage the module: Jumper Setting Description JP21 closed Pin 9 of DB-9 socket P1A connected with the SCLK0...

  • Page 82: Second Serial Interface At Socket P1B

    Jumper Setting Description closed Pin 2 of DB-9 socket P1B connected with RS-232 interface signal TxD1 of the phyCORE-TC1775 open Pin 9 of DB-9 socket P1B not connected open Pin 7 of DB-9 socket P1B not connected open Pin 4 of DB-9 socket P1B not connected...
  • Page 83 The phyCORE-TC1775 on the Development Board Caution: When using the DB-9 socket P1B as RS-232 interface on the phyCORE-TC1775 the following jumper settings are not functional and could damage the module: Jumper Setting Description closed Pin 9 of DB-9 socket P1B connected with the SCLK1...

  • Page 84: First Can Interface At Plug P2A

    Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1. CAN transceiver populating the phyCORE-TC1775 is enabled and the CAN signals from the module extend directly to plug P2A. Jumper...

  • Page 85: On Development Board)

    The phyCORE-TC1775 on the Development Board 2. The CAN transceiver populating the phyCORE-TC1775 is disabled; CAN signals generated by the CAN transceiver (U2) on the Development Board extending to connector P2A without galvanic seperation: Jumper Setting Description JP11 1 + 3...

  • Page 86: Figure 22: Pin Assignment Of The Db-9 Plug P2A (Can Transceiver On Development Board With Galvanic Separation)

    3. The CAN transceiver populating the phyCORE-TC1775 is disabled; CAN signals generated by the CAN transceiver (U2) on the Development Board extend to connector P2A with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 13 V. The external power supply must be only connected to either P2A or P2B.

  • Page 87: Second Can Interface At Plug P2B

    Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1. CAN transceiver populating the phyCORE-TC1775 is enabled and the CAN signals from the module extend directly to plug P2B. Jumper...

  • Page 88: Figure 24: Pin Assignment Of The Db-9 Plug P2B

    2. The CAN transceiver populating the phyCORE-TC1775 is disabled; CAN signals generated by the CAN transceiver (U3) on the Development Board extending to connector P2B without galvanic seperation: Jumper Setting Description JP14 1 + 3 Pin 7 of DB-9 plug P2B connected with CAN-H1 from...

  • Page 89: Figure 25: Pin Assignment Of The Db-9 Plug P2B (Can Transceiver On Development Board With Galvanic Separation)

    The phyCORE-TC1775 on the Development Board 3. The CAN transceiver populating the phyCORE-TC1775 is disabled; CAN signals generated by the CAN transceiver (U3) on the Development Board extend to connector P2B with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 13 V.

  • Page 90: Rj45 Ethernet Connector X7

    The phyCORE-TriCORE Development Board offers a programmable LED at D3 for user implementations. This LED can be connected to port pin P10.0 of the phyCORE-TC1775 which is available via signal GPIO0 (JP17 = closed). A low-level at port pin P10.0 causes the LED to illuminate, LED D3 remains off when writing a high-level to P10.0.

  • Page 91: Pin Assignment Summary Of The Phycore, The Expansion Bus And The Patch Field

    14.1, signals from phyCORE-TC1775 extend in a strict 1:1 assignment to the Expansion Bus connector X2 on the Development Board. These signals, in turn, are routed in a similar manner to the patch field on an optional expansion board that mounts to the Development Board at X2.

  • Page 92: Figure 26: Pin Assignment Scheme Of The Expansion Bus

    Figure 26: Pin Assignment Scheme of the Expansion Bus A B C D E F Figure 27: Pin Assignment Scheme of the Patch Field © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 93: Development Board / Expansion Board (Class B Pins Nominal 2.5 V, 3.3 V Tolerant)

    The phyCORE-TC1775 on the Development Board The pin assignment on the phyCORE-TC1775, in conjunction with the Expansion Bus (X2) on the Development Board and the patch field on an expansion board, is as follows: Signal phyCORE-TC1775 Expansion Bus Patch Field...

  • Page 94: Development Board / Expansion Board (Class B Pins Nominal 2.5 V, 3.3 V Tolerant)

    Signal phyCORE-TC1775 Expansion Bus Patch Field Table 24: Pin Assignment Address Bus for the phyCORE-TC1775 / Development Board / Expansion Board (Class B Pins Nominal 2.5 V, 3.3 V Tolerant) © PHYTEC Messtechnik GmbH 2004 L-538e_2...
  • Page 95 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 Table 25: Pin Assignment Port P3, P4, P5 Dedicated Port Pins on the phyCORE-TC1775/ Development Board / Expansion Board (Class B Pins Nominal 2.5 V, 3.3 V Tolerant) © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 96: Phycore-Tc1775 / Development Board Expansion Board (Maximum Voltage 5 V)

    79D, 77C, 74D, 72C 79D, 77C, 74D, Varef1 Vagnd1 69D, 67C, 64D, 69D, 67C, 64D, 62C, 59D 62C, 59D Table 26: Pin Assignment Analog Ports P6, P7 for the phyCORE-TC1775 / Development Board / Expansion Board (Maximum Voltage 5 V) © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 97: Phycore-Tc1775 / Development Board Expansion Board (Class A Pins Nominal 3.0 V To 5.25 V)

    P9.8 P9.9 P9.10 P9.11 P9.12 P9.13 P9.14 P9.15 Table 27: Pin Assignment Analog Ports P8, P9 for the phyCORE-TC1775 / Development Board / Expansion Board (Class A Pins Nominal 3.0 V to 5.25 V) © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 98: Phycore-Tc1775 / Development Board Expansion Board (Class A Pins Nominal 3.0 V To 5.25 V)

    P11.8 P11.9 P11.10 P11.11 P11.12 P11.13 P11.14 P11.15 Table 28: Pin Assignment Analog Ports P10, P11 for the phyCORE-TC1775 / Development Board / Expansion Board (Class A Pins Nominal 3.0 V to 5.25 V) © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 99: Phycore-Tc1775 / Development Board Expansion Board (Class A Pins Nominal 3.0 V To 5.25 V)

    P13.8/ MTSR0 P13.9/ SCLK1 P13.10/ MRST1 P13.11/ MTSR1 /HDRST Table 29: Pin Assignment Analog Ports P12, P13 for the phyCORE-TC1775 / Development Board / Expansion Board (Class A Pins Nominal 3.0 V to 5.25 V) © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 100: Phycore-Tc1775 / Development Board Expansion Board

    CLKOUT CLKIN /RESIN /BOOT CLKOUT_RTC /IRTC Table 31: Pin Assignment Control & Misc. Signals for the phyCORE-TC1775 / Development Board / Expansion Board Signal phyCORE-TC1775 Expansion Bus Patchfeld X1A50 Table 32: Freely Configurable Pins on the Optional PLD at U16 ©...
  • Page 101 Expansion Bus Patch Field 8C, 6D, 7D, 8D 8C, 6D, 7D, 8D 54D, 27F, 54F 39E, 46A, 3E, 2D, 2F, 3A Table 34: Unused Pins on the phyCORE-TC1775 / Development Board / Expansion Board © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 102: Ds2401 Silicon Serial Number

    Silicon Serial Number Table 35: JP16 Jumper Configuration for Silicon Serial Number Chip NUMPORT Port P10.1 connected JP16 Figure 28: Connecting the DS2401 Silicon Serial Number Figure 29: Pin Assignment of the DS2401 Silicon Serial Number © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 103: Pin Header Connectors X4 And X5

    The phyCORE-TC1775 on the Development Board 14.3.11 Pin Header Connectors X4 and X5 The pin headers X4 and X5 on the Development Board enable connection of an optional modem power supply. Connector X4 supplies 5 VDC at pin 1 and provides the phyCORE-TriCORE Development Board GND potential at pin 2.
  • Page 104 © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 105: Debugcore-Tc1775 On The Development Board

    Development Board The debugCORE-TC1775 is a special debugging version Single Board Computer (SBC) module which is 100 % function-compatible with the phyCORE-TC1775. As opposed to the phyCORE-TC1775, which was developed applications, debugCORE-TC1775 offers an additional 16-pin pin header at X2 in 2 mm spacing and a 40-pin AMP connector at X2.
  • Page 106 PC are established as follows: a) Connect the included ribbon cable (WF040) to the connector X3 on the phyCORE-TC1775 and to pin header X6 on the Development Board. Be sure that the red ribbon cable is connected to pin 1...
  • Page 107 The steps required for establishing the connections are: a) Connect the pin header X3 on the phyCORE-TC1775 with the JTAG input (OCDS1) on your debugger. b) Insert the debugger's trace adapter into the 40-pin socket connector...
  • Page 108 © PHYTEC Messtechnik GmbH 2004 L-538e_2...

  • Page 109: Revision History

    Version numbers Changes in this manual 01-April-2003 Manual L-538e_1 First edition. PCM-010 PCB# 1181.1 PCM-993 PCB# 1182.0 18-Mar.-2004 Manual L-538e_2 update to redesigned PCB version PCM-010 chapter about J1850 deleted PCB# 1181.2 PCM-993 PCB# 1182.0 © PHYTEC Messtechnik GmbH 2006 L-538e_3...

  • Page 110: Release Notes

    Changes in revision: PCB#1181.2 (phyCORE-TC1775): The features of the optional PLD at U16 are not described in this version of the manual. The PLD source code is still under construction at this point.
  • Page 111 Jumper Settings......32 serial........42 EMC..........1 LED D3 ........86 Ethernet EEPROM ....... 53 I/O Mode........ 51 MAC Address ......52 Memory Mode ....... 51 Memory Model Expansion Bus ......87 following Reset ...... 37 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 112 Reset Behavior......33 RJ45 .......... 86 RS-232 Interface....... 46 VBAT ........56 RS-232 Level......46 RS-232 Transceiver ....46 Weight........63 RTC .......... 43 X7 ..........86 SCL........... 54 SDA .......... 54 Second CAN Interface....83 © PHYTEC Messtechnik GmbH 2004 L-538e_2...
  • Page 113 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Messtechnik GmbH 2006 L-538e_3...
  • Page 114 Published by © PHYTEC Messtechnik GmbH 2006 Ordering No. L-538e_3 Printed in Germany...

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