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Phytec phyCORE-XC161 Hardware Manual

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phyCORE-XC161
Hardware Manual
Edition February 2004
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-XC161

  • Page 1 Hardware Manual Edition February 2004 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Meßtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Meßtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Table of Contents Preface ......................1 Introduction ..................3 1.1 Block Diagram................6 1.2 View of the phyCORE-XC161 .............7 Pin Description..................9 Jumpers ....................17 3.1 J1, J2 A/D Reference Voltage ...........23 3.2 J3 Internal or External Program Memory ........23 3.3 J4 SRAM U6/U7 Chip Select ............24 3.4 J5 SRAM Memory Size.............24...
  • Page 4 11.1 Fundamentals................53 11.2 Memory Mode ................53 Debug Interface ................. 55 Technical Specifications..............57 Hints for Handling the phyCORE-XC161 ........59 The phyCORE-XC161 on the phyCORE Development Board HD200 XC ................61 15.1 Concept of the phyCORE Development Board HD200..... 61 15.2 Development Board HD200 XC Connectors and Jumpers ..
  • Page 5 Table of Contents Index of Figures Figure 1: Block Diagram phyCORE-XC161 ..........6 Figure 2: View of the phyCORE-XC161 (Top View) .........7 Figure 3: View of the phyCORE-XC161 (Bottom View)......8 Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross Section Insert)................11 Figure 5: Numbering of the Jumper Pads...........17...
  • Page 6 Figure 28: Pin Assignment Scheme of the Expansion Bus......92 Figure 29: Pin Assignment Scheme of the Patch Field........ 92 Figure 30: Pin Assignment Control Signals for the phyCORE-XC161 / Development Board / Expansion Board ........97 Figure 31: Pin Assignment Power Supply for the phyCORE-XC161 / Development Board / Expansion Board ........
  • Page 7 Table 22: Functional Settings on Port P0 for System Startup Configuration................36 Table 23: System Startup Configuration Registers........38 Table 24: Bus Timing Calculation Examples ..........41 Table 25: Memory Device Options for U8 ..........49 Table 26: E²PROM/FRAM Write Protection ..........49 Table 27: E²PROM/FRAM Address............50 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 8 Table 42: Improper Jumper Settings for DB-9 Socket P1B (no Second RS-232) ..................79 Table 43: Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the phyCORE-XC161........80 Table 44: Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Development Board ........81 Table 45: Improper Jumper Settings for the CAN Plug P2A (CAN Transceiver on the Development Board)........
  • Page 9 Transceiver on Development Board with Galvanic Separation) ..............85 Table 49: Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the phyCORE-XC161 ........86 Table 50: Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Development Board ........87 Table 51: Improper Jumper Settings for the CAN Plug P2B (CAN Transceiver on the Development Board)........88...
  • Page 10 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 11: Preface

    (such as electricians, technicians and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows or connectors are longer than 3 meters.
  • Page 12 The phyCORE-XC161 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports...

  • Page 13: Introduction

    Introduction 1 Introduction The phyCORE-XC161 belongs to PHYTEC’s phyCORE Single Board Computer module family. The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a microcontroller...
  • Page 14 The phyCORE-XC161 is a subminiature (60 x 53 mm) insert-ready Single Board Computer populated with Infineon’s XC161CJ microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch (0.635 mm) connectors aligning two sides of the board, allowing it to be plugged like a “big chip”...
  • Page 15 • RS-232 transceiver for two serial interfaces • optional CS8900A 10Base-T Ethernet controller Please contact PHYTEC for more information about additional modul configurations. Number of available /CS signals depends on configuration of the phyCORE module. © PHYTEC Meßtechnik GmbH 2004...

  • Page 16: Block Diagram

    RxD0/TxD0 RS-232 RxD1/TxD1 Transceiver RxD1/TxD1 CAN0H/CAN0L CAN0 Transceiver CAN1H/CAN1L CAN1 Transceiver I/O Ports Ports I²C Bus I²C JTAG Port JTAG Port Reset Reset PROM JTAG RTC8564 MAX690A FRAM Connector Figure 1: Block Diagram phyCORE-XC161 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 17: View Of The Phycore-Xc161

    Introduction View of the phyCORE-XC161 Figure 2: View of the phyCORE-XC161 (Top View) © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 18: Figure 3: View Of The Phycore-Xc161 (Bottom View)

    Figure 3: View of the phyCORE-XC161 (Bottom View) © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 19: Pin Description

    (SMT) connectors (0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the phyCORE-XC161 to be plugged into any target application like a "big chip". A new numbering scheme for the pins on the phyCORE-connector has been introduced with the phyCORE specifications.
  • Page 20 Development Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus covered with the corner of the phyCORE-XC161 marked with a white triangle. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

  • Page 21: Figure 4: Pinout Of The Phycore-Connector (Top View, With Cross Section Insert)

    Pin Description The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-XC161 with SMT phyCORE- connectors on its underside (defined as dotted lines) mounted on a Development Board. In order to facilitate understanding of the pin...
  • Page 22 P3.0 CAPCOM1 Timer T0 Counter input P3.1 GPT12E Timer T6 latch output P3.3 GPT12E Timer T3 latch output P3.6 GPT12E Timer T3 counter input P6.0, /CS0 Chip Select #0 P6.1, /CS1 Chip Select #1 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 23 P7.7 CAPCOM2:CC31 Capture Input/Compare Output 42B, 43B, 45B, P3.8, P3.13, P3.2, Port 3 of the microcontroller (see corresponding 46B, 47B, 48B P3.4, P3.5, P3.7 Data Sheet) /CS_ETH Chip Select Ethernet Controller (refer to J26) © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 24 Battery input for back-up of RTC /PFO MAX 690/ Power Fail output BOOT Input for starting Bootstrap mode /RESET /RESET input of the phyCORE-XC161 /RESOUT /RESOUT signal of µC 13C, 14C, 15C P9.2, P9.4, P9.5 Port 9 of the microcontroller (see corresponding Data Sheet) 16C, 30C, 39C.

  • Page 25: Table 1 Pinout Of The Phycore-Connector X1

    MAX 690 power fail input. If this input is unused, it must be connected to VCC or GND MAX 690 Watchdog input /RESET /RESET input of the phyCORE-XC161 11D, 12D, 13D P9.0, P9.1, P9.3 Port 9 of the microcontroller (see corresponding...
  • Page 26 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 27: Jumpers

    Jumper 3 Jumpers For configuration purposes, the phyCORE-XC161 has 32 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the jumper pads, while Figure 7 indicates the location of the jumpers on the board.

  • Page 28: Figure 7: Location Of The Jumpers (Connector Side)

    Figure 7: Location of the Jumpers (Connector Side) © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 29 These pins are solely connected to GND of the Development Board when using the phyCORE module on a phyCORE Development Board HD200. It is not possible to attach an external GND potential in this configuration. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 30 U11 con- nected to P9.0 of the nected to Port P4.4 (A20) microcontroller (see of the microcontroller (see controller Data Sheet) controller Data Sheet) Note: Only applicable if on-board CAN transceivers are not populated. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 31 Note: Only applicable if on-board CAN transceivers are not populated. Note: These jumpers must remain closed on the phyCORE-XC161. If they are open, no serial communication is possible, hence PHYTEC FlashTools or the BOOT monitor will not function properly.

  • Page 32: Table 2: Jumper Settings

    (2 + 4) IRQ from Ethernet controller routed to P2.15 J32 (open) Boot sector of Flash at (closed) Flash write protected U4 not write protected active (refer to Flash data sheet) Table 2: Jumper Settings © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 33: J1, J2 A/D Reference Voltage

    Jumper 3.1 J1, J2 A/D Reference Voltage The A/D converter on the phyCORE-XC161 requires an upper and lower reference voltage connected at pins 41 and 42 (V AREF AGND The reference voltage source can be selected using Jumpers J1 and J2.

  • Page 34: J4 Sram U6/U7 Chip Select

    3.4 J5 SRAM Memory Size Jumper J5 configures the size of the SRAM devices installed at U6 and U7. If the phyCORE-XC161 is populated with external SRAM devices with a total capacity of 2*512 kByte, J5 must be closed at position 1+2.

  • Page 35: J6 E²Prom/Fram Supply Voltage

    Write protection of E²PROM/FRAM closed activated * = Default setting Table 8: J7 Write Protection of E²PROM/FRAM Refer to the corresponding E²PROM/FRAM Data Sheet for more information on the write protection function. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 36: J8, J9 Address Of The Serial E²Prom/ Fram

    The following configurations are possible: R1O TTL Level Signal at U14 open * Disconnected from Molex pin X1D15 Connected to Molex pin X1D15 (Plex) closed * = Default setting Table 10: J10 RS-232 Transceiver R1O TTL Output © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 37: J11, J12, J15, J16 Can Interfaces

    Jumper J11, J12, J15, J16 CAN Interfaces The first CAN interface of the phyCORE-XC161 is available at the port pins P4.5 (CAN0Rx) and P4.6 (CAN0Tx). The second CAN interface is located at port pins P4.4 (CAN1Rx) and P4.7 (CAN1Tx). The XC161 controller also offers a rerouting feature for CAN interface signals to port P9.

  • Page 38: J13, J14, J17, J18 Can Transceiver

    CAN signals with their TTL level are routed to the phyCORE Connector X1. Note: J13, J14, J17 and J18 are configured at time of delivery of the phyCORE module and must not be altered at a later time by the user. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 39: J19 Rtc Interrupt Output

    3.12 J20, J21 Configuration of P9.4 and P9.5 for I²C Bus The phyCORE-XC161 is equipped with a Real-Time Clock at U13 and a serial E²PROM/FRAM at U8. Both the Real-Time Clock and the serial E²PROM/FRAM are accessed by means of an I²C interface.

  • Page 40: J22 Rtc (U13) Clock Output

    TTL level at phyCORE-connector pins X1D17 and X1D16. Note: These jumpers must remain closed on the phyCORE-XC161. If they are open, no serial communication is possible, hence PHYTEC FlashTools or the BOOT monitor will not function properly.

  • Page 41: J25, J26 Second Serial Interface

    RS-232 level P3.0 and P3.1 available as I/O pins open open at X1A45 and X1A44 Not allowed! 1 + 2 1 + 2 * = Default setting Table 16: J25, J26 Second Serial Interface Configuration © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 42: J27 Ethernet Controller Chip Select

    J27 Ethernet Controller Chip Select Jumper J27 configures the source of the Chip Select signal that controls the Ethernet controller. Configuration of J27 also depends on the module configuration of the phyCORE-XC161. The following configurations are possible: Chip Select for Ethernet Controller...

  • Page 43: J29 Ethernet Controller Sleep Mode

    X1D37, X1D25 und X1D26 P2.13 connected to IRQ_ETH 1 + 2 P2.14 connected to IRQ_ETH 2 + 3 P2.15 connected to IRQ_ETH 2 + 4 * = Default setting Table 20: J30 Ethernet Controller IRQ Signal Configuration © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 44: J32 Write Protection Of Flash

    Write protection of Flash deactivated Write protection of Flash activated closed * = Default setting Table 21: J32 Write Protection of Flash ___________________ Refer to the corresponding Flash Data Sheet for more information on the write protection function. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 45: System Configuration

    The system startup configuration can be set by connecting desired pins at port 0 with a pull-down resistor (resulting in logical 0), or by leaving the connections open (resulting in logical 1). © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 46: Table 22: Functional Settings On Port P0 For System Startup Configuration

    (logical 1). Configuration on these pins must not be changed. On modules with a memory configuration featuring 2 MByte Flash memory the register SALSEL must be configured with the values 1 (H4) 0 (H3). © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 47 /WR and /BHE pins /WR and P3.12 On modules with a memory configuration featuring 2 MByte Flash memory the register SALSEL must be configured with the values 1 (H4) 0 (H3). © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 48: Table 23: System Startup Configuration Registers

    Table 23: System Startup Configuration Registers Default system startup configuration of the phyCORE-XC161 The initial setting of the system startup configuration can be modified during the initialization routine. Certain functions can not be con- figured during startup, such as selection of the number of wait states for individual memory devices and Chip Select signals, as well as the location of these devices within the controller’s address space.

  • Page 49: Memory Models

    P6 for easy selection of external peripherals or memory banks. Depending on the number of memory devices installed on the phyCORE-XC161, as well as the availability of the Ethernet controller, up to four Chip Select signals are used internally. /CS0 (P6.0) selects the Flash memory installed on U4 with a total memory of either 256 kByte, 512 kByte, 1 MByte or 2 MByte.

  • Page 50: Figure 8: Timing Phases For Multiplexed Bus Mode

    4 ns have to be considered. The H-to-L transitions delay for /CS, /RD and /WR signals can be as long as 10 ns while the rise time (L-to-H) for the same signals can be up to 6 ns. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 51: Table 24: Bus Timing Calculation Examples

    Demultiplexed bus at 40 MHz Memory TCONCSx PHA PHB PHC PHD PHE RDPHF WRPHF SRAM 0x0040 15ns, U5 Flash 0x0080 70ns, U4 SRAM 0x0080 70ns, U6/7 Ethernet at 0x240 Table 24: Bus Timing Calculation Examples © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 52: Bus Cycle Phases

    The C phase is similar to the A and B phases but ALE is already low. It can take 0-3 clocks. In multiplexed bus mode, the address is held in order to be latched safely. Phase C cycles can be used to delay the command signals (R/W delay). © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 53 F phase is independently programmable for read and write accesses. The F phase is used to program tristate wait states on the bidirectional data bus in order to avoid bus conflicts. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 54 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 55: Serial Interfaces

    RS-232 transceiver not located on the module. Note: Jumpers J23 and J24 must remain closed on the phyCORE-XC161. If they are open, no serial communication is possible, hence PHYTEC FlashTools or the BOOT monitor will not function properly.

  • Page 56: Can Interface

    6.2 CAN Interface The phyCORE-XC161 is designed to house two CAN transceivers at U10 and U11 (either PCA82C251 or TLE6250). The CAN bus transceiver devices support signal conversion of the CAN transmit (CANTx) and receive (CANRx)lines. The CAN transceiver supports up to 110 nodes on a single CAN bus.

  • Page 57: Real-Time Clock Rtc-8564 (U13)

    • 24-hour format • Automatic word address incrementing • Programmable alarm, timer and interrupt functions If the phyCORE-XC161 is buffered by battery, the Real-Time Clock runs independently of the board’s power supply. Programming the Real-Time Clock is done via the I C bus (address 0xA2 = 10100010), which is connected to port P9.5 (SCL)
  • Page 58 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 59: Serial E²Prom/Fram (U8)

    Serial E²PROM/FRAM 8 Serial E²PROM/FRAM (U8) The phyCORE-XC161 is populated with a non-volatile memory with a serial interface (I C interface) to store configuration data. According to the memory configuration of the module, an E²PROM (4 to 32 kByte) or FRAM can be mounted at U8.

  • Page 60: Table 27: E²Prom/Fram Address

    2 + 3 0xAC 2 + 3 1 + 2 * = Default setting Table 27: E²PROM/FRAM Address ______________________ Refer to the corresponding E²PROM/FRAM Data Sheet for more information on the write protection function. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 61: Flash Memory (U4)

    Flash Memory Flash Memory (U4) Use of Flash as non-volatile memory on the phyCORE-XC161 provides an easily reprogrammable means of code storage. The following Flash devices can populate the phyCORE-XC161: • 29F200 with 1* 16 kByte, 2* 8 kByte, 1* 32 kByte, 3* 64 kByte •...

  • Page 62: Battery Buffer And Voltage Supervisor Chip (U9)

    The VBAT input at pin X1C6 of the board is provided for connecting the external battery. The negative polarity pin on the battery must be connected to GND on the phyCORE-XC161. As of the printing of this manual, a lithium battery is recommended as it offers relatively high capacity at low discharge.

  • Page 63: Cs8900A Ethernet Controller

    11.1 Fundamentals The CS8900A is a IEEE 802.3 Single-Chip Ethernet-Controller that is operated in memory mode on the phyCORE-XC161. The configuration data for the Ethernet controller are stored in a E²PROM located at U22. The CS8900A Ethernet controller provides the following features: •...
  • Page 64 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 65: Debug Interface

    Debug Interface Debug Interface The phyCORE-XC161 is equipped with a JTAG interface for downloading program code into the external Flash or for debugging programs in the external SRAM. The JTAG interface extends to 2 mm pitch pin header pads at X2 located on the controller side of the module.

  • Page 66: Figure 11: Jtag Interface (Bottom View)

    Note: The JTAG connector X2 is usually not populated on standard versions of the phyCORE-XC161 modules since they are intended for OEM implementation. The applicable pin header connector for X2 is available through PHYTEC (order code VL094) and included in all Rapid Development Kits (order code KPCM-020).

  • Page 67: Technical Specifications

    Technical Specifications 13 Technical Specifications The physical dimensions of the phyCORE-XC161 are represented in Figure 12. The module’s profile is ca. 6 mm thick, with a maximum component height of 2.0 mm on the backside of the PCB and approximately 2.5 mm on the front side. The board itself is approximately 1.6 mm thick.
  • Page 68 20°C maximum 100 µA VCC = 0 V, VBAT = 3 V, typ. 1 µA Real-Time Clock 20°C These specifications describe the standard configuration of the phyCORE-XC161 as of the printing of this manual. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 69: Hints For Handling The Phycore-Xc161

    Hints for Handling the Module 14 Hints for Handling the phyCORE-XC161 All XC161 compatible controllers can populate the phyCORE-XC161 module at U1. Please note that, if using a XC161 derivative with an active CAN interface at port 4, only 20 external address lines (A0…A19) and 1 MByte of address space is available on the module.
  • Page 70 Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 71: The Phycore-Xc161 On The Phycore Development Board Hd200 Xc

    The phyCORE-XC161 on the Development Board The phyCORE-XC161 on the phyCORE Development Board HD200 XC PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start- up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules.

  • Page 72: Figure 13: Modular Development And Expansion Board Concept With The Phycore-Xc161

    • As the physical layout of the expansion bus is standardized across all applicable PHYTEC Development Boards, we are able to offer various expansion boards (5) that attach to the Development Board at the expansion bus connectors. These modular expansion...

  • Page 73: Development Board Hd200 Xc Connectors And Jumpers

    The phyCORE-XC161 on the Development Board 15.2 Development Board HD200 XC Connectors and Jumpers 15.2.1 Connectors As shown in Figure 14, the following connectors are available on the phyCORE Development Board HD200 XC: low-voltage socket for power supply connectivity mating receptacle for expansion board connectivity...
  • Page 74 Sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 75: Figure 15: Numbering Of Jumper Pads

    The Development Board’s peripheral components are configured for use with the phyCORE-XC161 by means of insertable jumpers. If no jumpers are set, no signals connect to the DB-9 connectors, the control and display units and the CAN transceivers. The Reset input on the phyCORE-XC161 directly connects to the Reset button (S2).

  • Page 76: Figure 17: Default Jumper Settings Of The Phycore Development Board Hd200 Xc With Phycore-Xc161

    Figure 17 shows the factory default jumper settings for operation of the phyCORE Development Board HD200 XC with the standard phyCORE-XC161 (standard = XC161 controller, use of two RS-232 interfaces, two CAN interfaces, LED D3, the Boot button on the Development Board).

  • Page 77: Unsupported Features And Improper Jumper Settings

    DB-9 plug P2B on the Development Board can be configured as RS-485 interface as an alternative to a possible second CAN interface. The phyCORE-XC161 does not support an RS-485 interface. For this reason the corresponding jumper settings should never be used.

  • Page 78: Functional Components On The Phycore Development Board Hd200 Xc

    Development Board HD200 XC GND potential. This makes a separate supply with an alternative VAGND potential impossible. Jumper J2 on the phyCORE-XC161 is therefore without function when the module is mounted on a Development Board HD200 XC. Free definition of the VAGND potential is however available in a customer application board.

  • Page 79: Power Supply At X1

    Permissible input voltage: +/-5 VDC regulated. The required current load capacity of the power supply depends on the specific configuration of the phyCORE-XC161 mounted on the Development Board as well as whether an optional expansion board is connected to the Development Board. An adapter with a minimum supply of 500 mA is recommended.

  • Page 80: Table 31: Jp9, Jp16 Improper Jumper Settings For The Supply Voltages

    JP9, JP16 Improper Jumper Settings for the Supply Voltages Setting Jumper JP9 to positions 1+2 configures a main power supply to the phyCORE-XC161 of 2.5 V which could destroy the module. If Jumper JP9 is open, no main power supply is connected to the phyCORE-XC161.

  • Page 81: Activating The Bootstrap Loader

    Reset signal changes from its active to the inactive state. This is achieved by applying a high-level signal at pin X1C9 of the phyCORE-XC161 as the Boot input is high-active. The phyCORE Development Board HD200 XC provides three different options to activate the on-chip Bootstrap Loader: 1.

  • Page 82: Table 33: Jp28 Configuration Of A Permanent Bootstrap Loader Start

    2. The Boot input of the phyCORE-XC161 can also be permanently connected to VCC via a pull-up resistor. This pulls the data line D4 to low level via an on-board circuitry which then starts the Bootstrap Loader. This spares pushing the Boot button during a hardware reset or power-on.

  • Page 83: First Serial Interface At Socket P1A

    Figure 19: Pin Assignment of the DB-9 Socket P1A as First RS-232 (Front View) This jumper should always be closed because communication with PHYTEC FlashTools requires use of the first serial interface on the phyCORE module. Alternative jumper configuration for additional features (refer to section 15.3.2). Not required for standard communication functions.

  • Page 84: Table 37: Improper Jumper Settings For Db-9 Socket P1A As

    Caution: When using the DB-9 socket P1A as RS-232 interface on the phyCORE-XC161 the following jumper settings are not functional and could damage the module: Jumper Setting Description JP20 open Pin 2 of DB-9 socket P1A not connected, no...

  • Page 85: Power Supply To External Devices Via Socket P1A

    The phyCORE-XC161 on the Development Board 15.3.4 Power Supply to External Devices via Socket P1A The phyCORE Development Board HD200 XC can be populated by additional components that provide a supply voltage of 5 V at pin 6 of DB-9 socket P1A. This allows for easy and secure supply of external devices connected to P1A.

  • Page 86: Table 38: Jp24 Power Supply To External Devices Connected To P1A On The Development Board

    JP24 2 + 3 Electronically protected 5 V at pin 6 for supply of external devices connected to P1A Table 38: JP24 Power Supply to External Devices Connected to P1A on the Development Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 87: Second Serial Interface At Socket P1B

    Socket P1B is the upper socket of the double DB-9 connector at P1. P1B is connected via jumpers to the second serial interface of the phyCORE-XC161. Depending on the module configuration (refer to section 3.15) and different options are available for configuration of socket P1B.

  • Page 88: Table 40: Improper Jumper Settings For Db-9 Socket P1B

    Caution: When using the DB-9 socket P1B as RS-232 interface on the phyCORE-XC161 the following jumper settings are not functional and could damage the module: Jumper Setting Description closed Pin 9 of DB-9 socket P1B connected with /TRST signal...

  • Page 89: Table 42: Improper Jumper Settings For Db-9 Socket P1B (No Second Rs-232)

    The phyCORE-XC161 on the Development Board Caution: When using the DB-9 socket P1B with the configuration of the phyCORE-XC161 as described above, the following jumper settings are not functional and could damage the module: Jumper Setting Description closed No TxD1_RS232 signal available from the...

  • Page 90: First Can Interface At Plug P2A

    Plug P2A is the lower plug of the double DB-9 connector at P2. P2A is connected to the first CAN interface (CAN0) of the phyCORE-XC161 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1.

  • Page 91: Table 44: Jumper Configuration For Can Plug P2A Using The Can Transceiver On The Development Board

    The phyCORE-XC161 on the Development Board 2. The CAN transceiver populating the phyCORE-XC161 is disabled; CAN signals generated by the CAN transceiver (U2) on the Development Board extending to connector P2A without galvanic seperation: Jumper Setting Description JP31 1 + 2...

  • Page 92: Figure 22: Pin Assignment Of The Db-9 Plug P2A

    Setting Description JP31 2 + 3 Pin 2 of DB-9 plug P2A connected with CAN-L0 from on-board transceiver on the phyCORE-XC161 JP32 2 + 3 Pin 7 of DB-9 plug P2A connected with CAN-H0 from on-board transceiver on the phyCORE-XC161...

  • Page 93: Galvanic Separation

    The phyCORE-XC161 on the Development Board 3. The CAN transceiver populating the phyCORE-XC161 is disabled; CAN signals generated by the CAN transceiver (U2) on the Development Board extend to connector P2A with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 28 V.

  • Page 94: Figure 24: Pin Assignment Of The Db-9 Plug P2A

    VCAN+ Pin 3: VCAN- Pin 7: CAN-H0 (galvanically separated) Pin 2: CAN-L0 (galvanically separated) Pin 6: VCAN- Figure 24: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver on Development Board with Galvanic Separation) © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 95 The phyCORE-XC161 on the Development Board Caution: When using the DB-9 plug P2A as CAN interface, and the CAN transceiver on the Development Board with galvanic separation, the following jumper settings are not functional and could damage the module: Jumper...

  • Page 96: Second Can Interface At Plug P2B

    Plug P2B is the upper plug of the double DB-9 connector at P2. P2B is connected to the second CAN interface (CAN1) of the phyCORE-XC161 via jumpers. Depending on the configuration of the CAN transceivers and their power supply, the following three configurations are possible: 1.

  • Page 97: Figure 26: Pin Assignment Of The Db-9 Plug P2B (Can Transceiver On Phycore-Xc161)

    The phyCORE-XC161 on the Development Board 2. The CAN transceiver populating the phyCORE-XC161 is disabled; CAN signals generated by the CAN transceiver (U3) on the Development Board extending to connector P2B without galvanic seperation: Jumper Setting Description JP33 2 + 3...

  • Page 98: Table 51: Improper Jumper Settings For The Can Plug P2B (Can Transceiver On The Development Board)

    Pin 2 at P2B is connected with P9.5 from the phyCORE-XC161 2 + 4 Pin 2 at P2B is connected with CAN_L1 from the on-board CAN transceiver on the phyCORE-XC161 JP34 2 + 3 Pin 7 at P2B is connected with CAN_H1 from the...

  • Page 99: Transceiver On The Development Board With Galvanic Separation

    The phyCORE-XC161 on the Development Board 3. The CAN transceiver populating the phyCORE-XC161 is disabled; CAN signals generated by the CAN transceiver (U3) on the Development Board extend to connector P2B with galvanic separation. This configuration requires connection of an external CAN supply voltage of 7 to 28 V.

  • Page 100: Figure 27: Pin Assignment Of The Db-9 Plug P2B

    Pin 2 at P2B is connected with P9.5 from the phyCORE-XC161 2 + 4 Pin 2 at P2B is connected with CAN_L1 from the on-board CAN transceiver on the phyCORE-XC161 JP34 2 + 3 Pin 7 at P2B is connected with CAN_H1 from the...

  • Page 101: Programmable Led D3

    LED at D3 for user implementations. This LED can be connected to port pin P9.0 of the phyCORE-XC161 which is available via signal GPIO0 (JP17 = closed). A low-level at port pin P9.0 causes the LED to illuminate, LED D3 remains off when writing a high-level to P9.0.

  • Page 102: Figure 28: Pin Assignment Scheme Of The Expansion Bus

    Figure 28: Pin Assignment Scheme of the Expansion Bus A B C D E F Figure 29: Pin Assignment Scheme of the Patch Field © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 103: Phycore-Xc161 / Development Board Expansion Board

    The phyCORE-XC161 on the Development Board The pin assignment on the phyCORE-XC161, in conjunction with the Expansion Bus (X2) on the Development Board and the patch field on an expansion board, is as follows: Signal phyCORE-XC161 Expansion Bus Patch Field P0L.0/D0...

  • Page 104: Phycore-Xc161 / Development Board Expansion Board

    P3.3/T3OUT/TDO P3.4/T3EUD/TMS P3.5/T4IN/ /BRKOUT 47B P3.6/T3IN P3.7/T2IN/ /BRKIN P3.8/MRST P3.9/MTSR P3.10/TxD0_TTL P3.11/RxD0_TTL P3.12/ /WRH /BHE P3.13/SCLK P3.15/CLKOUT Table 56: Pin Assignment Port P2, P3, P4 for the phyCORE-XC161 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 105: Phycore-Xc161 / Development Board Expansion Board

    P6.5/ /HOLD P6.6/ /HLDA P6.7/ /BREQ P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P9.0/CAN2_RxD P9.1/CAN2_TxD P9.2/CAN1_RxD P9.3/CAN1_TxD P9.4/CC20IO P9.5/CC21IO Table 57: Pin Assignment Port P5, P6, P7, P9 for the phyCORE-XC161 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 106: Phycore-Xc161 / Development Board Expansion Board

    CAN-H1 CAN-L1 RxD0_RS232 TxD0_RS232 RxD1_RS232 TxD1_RS232 RxD0_TTL TxD0_TTL RxD1_TTL TxD1_TTL /BRKIN /BRKOUT /TRST ETH_LINKLED ETH_LANLED ETH_RxD+ ETH_TxD+ ETH_RxD- ETH_TxD- Table 58: Pin Assignment Interface Signals for the phyCORE-XC161 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 107: Figure 30: Pin Assignment Control Signals For The Phycore-Xc161 / Development Board / Expansion Board

    Expansion Bus Patch Field /ALE /CS_ETH /IRQ_ETH /IRQ_RTC /NMI /PFO /RESET 10C, 10D 10C, 10D 3D, 3F /RSTOUT /WR/ /WRL BOOT RTC_CLKOUT Figure 30: Pin Assignment Control Signals for the phyCORE-XC161 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 108: Figure 31: Pin Assignment Power Supply For The Phycore-Xc161 / Development Board / Expansion Board

    41D, 42D, 43D, 39D, 44D, 49D, 46D, 47D, 48D, 54D, 59D, 64D, 51D, 52D, 53D, 69D, 74D, 79D 1E, 2E, 1F Figure 31: Pin Assignment Power Supply for the phyCORE-XC161 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 109: Figure 32: Unused Pins On The Phycore-Xc161 / Development Board / Expansion Board

    70D, 71D, 72D, 25F, 26F, 27F, 73D, 75D, 76D, 44F, 45F, 46F, 77D, 78D, 80D 47F, 48F, 49F, 50F, 51F, 52F, 53F, 54F Figure 32: Unused Pins on the phyCORE-XC161 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 110: Battery Connector Bat1

    Voltage Supervisor Chip phyCORE-XC161 is responsible for switching from a normal power supply to a back-up battery. The optional battery required for this function (refer to section 10) is available through PHYTEC (order code BL-011). 15.3.11 Releasing the /NMI Interrupt...

  • Page 111: Pin Header Connector X4

    The phyCORE-XC161 on the Development Board NUMPORT Port P9.1 connected JP19 Figure 35: Connecting the DS2401 Silicon Serial Number Figure 36: Pin Assignment of the DS2401 Silicon Serial Number 15.3.13 Pin Header Connector X4 The pin header X4 on the Development Board enables connection of an optional modem power supply.

  • Page 112: Jp40, S3 Multi-Purpose Push Button Configuration

    S3 connected with /NMI (BUS5) signal of the XC161 1 + 2 microcontroller S3 connected with P2.10/EX2IN (BUS4) signal of the 2 + 3 XC161 microcontroller * = Default setting Figure 37: JP40 Multi-Purpose Push Button S3 Configuration © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 113: Ethernet Port

    Ethernet Port 16 Ethernet Port The phyCORE Development Board HD200 XC provides a 10-pin header connector at X7 for mounting the PHYTEC Ethernet transformer module. The optional add-on module is available through PHYTEC (order code EAD-001). Figure 38: Ethernet Transformer Module Connector...

  • Page 114: Figure 40: Jumper For Ethernet Transformer Port

    The insertable jumpers JP37 und JP38 on the phyCORE Development Board HD200 XC are provided for compatibility reasons in support of the phyCORE-167CR/CS (PCM-009): Jumper phyCORE-XC161 phyCORE-XC161 in compatibility mode phyCORE-167CR/CS JP37 1 + 2 2 + 3 JP38...

  • Page 115: Revision History

    Figure 3 and Figure 7. PCB# 1214.1 New images showing the 1179.5 PCB revision in PCM-997-XC section 15. PCB# 1179.5 Description for new push button S3 and Jumper JP40 added in new section 15.3.14. © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 116 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...

  • Page 117: Index

    Functional Components on the Concept of the Development phyCORE Board ........71 Development Board....80 Connector X4 ......117 CS8900A ........63 Humidity........68 Debug Interface......65 Development Board C Bus ........55 Connectors and Jumpers ..74 I²C Bus........32 Dimensions........68 C Interface ......58 DS2401........115 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 118 Reference Voltage..... 23 JP40......... 118 Reset Button ......76 JTAG Interface......65 RS-232 ........ 34, 36 Jumper........17 RS-232 Interface ....... 52 Jumper Configuration ....76 RS-232 Level ......52 Jumper Settings ......22 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 119 VBAT ........62 Socket P1A (First RS-232)..85 Voltage Supervisor Chip ...62 Socket P1B (Second RS-232) ...90 VPD ...........62 SRAM ........25 Storage Temperature ....68 System Configuration....41 Weight ........68 System Initialization....41 System Startup X2 ..........65 Configuration ......41 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 120 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 121 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Meßtechnik GmbH 2004 L-622e_4...
  • Page 122 Published by © PHYTEC Meßtechnik GmbH 2004 Ordering No. L-622e_4 Printed in Germany...

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