Phytec phyCORE-PXA255 Hardware Manual

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Development Board for

phyCORE-PXA255

Hardware Manual

PCB# 1220.1 and 1220.2

Edition November 2004

A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-PXA255

Page 1 Development Board for phyCORE-PXA255 Hardware Manual PCB# 1220.1 and 1220.2 Edition November 2004 A product of a PHYTEC Technology Holding company...
Page 2 PHYTEC Meßtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Meßtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.
Page 3 Push Buttons and LEDs ..............65 Matrix Keyboard................67 GPIO Expansion Board Interface............69 JTAG Interface (X29) ...............85 Technical Specifications..............87 Hints for Handling the Module ............89 Component Placement Diagram ............91 Revision History ................92 Appendices A ....................93 Hardware Revision ..............93 Index ......................95 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 4 Development Board for phyCORE-PXA255 Index of Figures Figure 1: Block Diagram of the Development Board........6 Figure 2: Development Board Overview (Top View) ........7 Figure 3: Development Board Overview (Connector Side View)....7 Figure 4: Expansion Board Overview (Top View)........8 Figure 5: Expansion Board Overview (Side View) ........
Page 5 Table 1: Port Configuration GPIO0-39 .............10 Table 2: Port Configuration GPIO40-84 ...........11 Table 3: Jumper Functions and Section Reference........14 Table 4: Interrupt Assignment phyCORE-PXA255 ........20 Table 5: Interrupt Assignment Development Board........20 Table 6: Control PLD U6 Reset Values ............22 Table 7: PLD U6 Control Register 0 ............22 Table 8: PLD U6 Control Register 1 ............23...
Page 6 Development Board for phyCORE-PXA255 Table 12: PLD U6 Control Register 5............25 Table 13: PLD U6 Control Registers 6 and 7..........25 Table 14: PLD U6 Control Register 8............26 Table 15: PLD U6 Control Register 9............27 Table 16: PLD U6 Control Register 10............27 Table 17: PLD U6 Control Register 11............
Page 7 Table 44: Expansion Board Connector X30 Pinout ........62 Table 45: Expansion Board Connector X31 Pinout ........63 Table 46: GPIO Expansion Bus X17 Pin Assignment ........77 Table 47: Signal Pin Assignment for the phyCORE-PXA255 Development Board / Expansion Board ........84 Table 48: JTAG Connector X29 Pinout ............85 ©...
Page 9 Preface Preface This manual describes only the functions of the PHYTEC phyCORE-PXA255 Development Board. The controllers and relevant Single Board Computers for use with the Development Board are not described herein. Additional controller- and board-level information and technical descriptions can be found in appropriate Hardware Manual or User’s Manual support documentation.
Page 10 Magnetic Directives. Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems. The phyCORE-PXA255 Development Board is one of a series of PHYTEC Development Boards supporting the phyCORE-PXA255 Single Board Computer module. PHYTEC supports common 8-, 16-...
Page 11 The hardware manual for this Development Board does not describe the features and functions of the phyCORE-PXA255 SBC module, as this is not relevant for the basic functioning of the Development Board. For module and controller-specific features please refer to the corresponding Hardware Manuals/User’s Manuals.
Page 12 12V). supplies regulated +3.3 V phyCORE-PXA255. Additional +5 V is created for the IDE and CF card and LCD/inverter circuitry. • Optional battery charger circuitry for NiMH batteries • Power magement for MMC, CF, IDE and LC display • Two user programmable LEDs •...
Page 13 Introduction • PXA255 Operating Systems Kits: Linux WinCE • phyCORE-PXA255 Debugging Systems: iSYSTEM iC3000 Active Emulator © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 14 Development Board for phyCORE-PXA255 1.1 Block Diagram Face Plate GPIO Reset LED D1-D5 GPIO-Taster USB-OTG Button Button COMPACT-FLASH PCMCIA IDE/CF PLD IDE 2,5" phyCORE-PXA255 X17 Port DATA/ADDR phyCORE-PXA250 xDATA/xADDR xDATA xADDRES Control PLD GPIO GPIO Button PWM0 Inverter TFT-LCD RGB + Pixel + Frame + Line + Enable...
Page 15 Figure 2: Development Board Overview (Top View) Expansion Board RESET Button 2 * USB Power Host Ethernet AC97 Socket Client FF-UART BT-UART Touch Connect Touch Panel Figure 3: Development Board Overview (Connector Side View) © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 16 Development Board for phyCORE-PXA255 X3 Connector to Base Board SOUND X4 Connector to Base Board Reset Botton MultiMedia Card GPIO Botton D5 D4 D2 D1 CompactFlash Card Figure 4: Expansion Board Overview (Top View) Taster Botton GPIO Botton MultiMedia Card...
Page 17 • FF-UART, BT-UART and IR-UART • SSP and NSSP • I²C bus Either the operating system installed on the phyCORE-PXA255 or the boot loader (e.g. U-Boot) must initialize the port pins in questions as shown in the table below: Port...
Page 18 Development Board for phyCORE-PXA255 GPIO17 PWM1 as clock signal GPIO18 Controller READY inut GPIO19 DREQ0 GPIO20 DREQ1 GPIO21 GPIO21 output for RUN LED GPIO22 GPIO22 output for BUSY LED GPIO23 SSPCLK SSP clock for EGPIO GPIO24 SFRM SPI FRAME signal as /CS_EGPIO (MAX7301)
Page 19 /CS3 16-bit VLIO for PLD GPIO80 /CS4 16-bit VLIO for ISP1362 USB Controller GPIO81 NSSP-CLK for CAN GPIO82 NSSP-FRAM as /CS_CAN (MPC2515) GPIO83 NSSP-TXD for CAN GPIO84 NSSP-RXD for CAN Table 2: Port Configuration GPIO40-84 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 21 Jumpers 3 Jumpers For configuration purposes, the phyCORE-PXA255 Development Board has 7 removable and 8 solder jumpers, most of which have been installed prior to delivery depending on the board’s configuration. Solder jumpers should not be changed by the user.
Page 22 Development Board for phyCORE-PXA255 Figure 8: Location of the Jumpers (Expansion Board) Description of the jumper functions is provided in the following manual sections. The jumpers are grouped by function as follows: Jumper Function/Section JP3, JP5, JP6, JP9 USB host Interface, refer to section 7...
Page 23 24 VDC. The on-board voltage converters generate all supply voltages required for the components on the Development Board, the Expansion Board and the phyCORE-PXA255. The supply voltage can also be used for the optional battery charger circuitry. Supply voltage 1: +3.3 V (VCC)
Page 24 Development Board for phyCORE-PXA255 Figure 9: Power Supply Block Diagram © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 25 It will charge the batteries when the Development Board is supplied with voltage by a wall adapter. Figure 10: Battery Charger Circuitry Note: The battery charger register is only available with PCB revision 1220.2 and higher. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 27 Memory Configuration 5 Memory Configuration The Development Board for the phyCORE-PXA255 uses the /CS signals /CS2 and /CS3 as well as the PCMCIA interface for controlling the components on the data bus. The other /CS signals on the phyCORE-PXA255 are controlled by the address decoder (control PLD U7) in order to connect the data bus driver.
Page 28 Development Board for phyCORE-PXA255 5.1 Interrupts The interrupt signals of the components on the phyCORE-PXA255 are configured on the phyCORE module itself. Because of the limited number of available GPIOs, the functions /MMC_DET and MMC-WP cannot be connected to GPIO7 and GPIO10 on the phyCORE module.
Page 29 /CS_3. The bus width is set to 16-bit as a VLIO interface. The registers of the Control PLD are listed in the following table. The register's reset value after the system start is shown below the description. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 30 The reset properties for RES_DEV on the Development Board are set in control register 0. RES_DEV is the reset signal that only affects the USB, CAN and Ethernet controller of the phyCORE-PXA255. Therefore it is possible to use the RESETOUT of the PXA255 controller in watchdog mode without having to reinitialize these controllers.
Page 31 PLD U6 Control Register 2 LEDPWR Setting this bit will turn on user LED D11. LEDUSR Setting this bit will turn on user LED D12. LEDBAS Setting this bit will turn on user LED D15. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 32 LCD data and control bus are switched active connected. LCDPWR Setting this bit turns on the supply voltage for the TFT display. Control register controls external supply voltage MultiMediaCard 1 on the phyCORE-PXA255. ADDR D7-D4 CTRL 4 0x0c000008 MMC1PWR R/W=0 R/W=0 R/W=0 R/W=0 Table 11:...
Page 33 The interrupt sources correspond to the designations of control register 7. ADDR D7-D4 CTRL 6 0x0c00000C INT3 INT2 INT1 INT0 R/W=0 CTRL 7 0x0c00000E PM_5V MMCDET FF_RI BT_DET R/W=0 Table 13: PLD U6 Control Registers 6 and 7 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 34 Development Board for phyCORE-PXA255 INT0 IRQ status bit for BT-UART detect INT1 IRQ status bit for FF-UART detect INT2 IRQ status bit for MMC-Card 2 detect INT3 IRQ status bit for 5 V power not present Clear bit = interrrupt active if one of the four bit = 0 => /INT0-BIT...
Page 35 /FL_DIS This bit can be used to disable the on-board Flash on the phyCORE-PXA255. This bit is active low AC97_ENA This bit controls an output signal routed to the AC97 expansion connector. It can be used to turn the supply voltage for an AC97 module connected to X24 on or off.
Page 36 Development Board for phyCORE-PXA255 The optional battery charger circuitry is configured with control register 11. Note: The battery charger register is only available with PCB revision 1220.2 and higher. ADDR D7-D4 0x0c000016 ALARM ACPRES ACSEL ACENA CTRL 11 R/W=0 Table 17:...
Page 37 Memory Configuration 5.2.2 External Data and Address Bus The data and address bus on the phyCORE-PXA255 operates with a clock frequency of 100 MHz, therefore it must be decoupled for external use. All components on the Development Board except the Control PLD are connected to the decoupled data and address bus.
Page 38 Development Board for phyCORE-PXA255 5.3 IDE Interface and CF Card PLD (U7) The phyCORE-PXA255 provides a PCMCIA interface that supports two independent PCMCIA sockets. The first socket is available on the Development Board as an IDE interface, the second interface extends as a CF card socket to the Expansion Board.
Page 39 2.0 mm header connector is located at X20 on the Development Board. Mounting holes for attaching the hard drive are located on the Development Board. The hard disk will be attached to the board using spacers above of the phyCORE-PXA255 module (refer to Figure 14 for details). JTAG Interface...
Page 40 Development Board for phyCORE-PXA255 Figure 15: IDE Circuitry The PCMCIA interface settings are made in the PXA255 controller. The IDE register of the PLD U7 along with their reset values are given in the following table. ADDR 0x2001000 PM_5V IDE 0...
Page 41 RDY signal. ADDR IDE 2 0x2001004 /IDE_RES Table 21: IDE Register 2 /IDE_RES Low active reset signal for the hard drive. /RDY Shows current state of the hard drive Ready signal. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 42 Development Board for phyCORE-PXA255 The IDE interface is separated from the data, address and control bus by line driver circuits. The drivers for the data bus can be activated with the signal IDEOE. IDEON activates the drivers for the address and control signal outputs and IDEIN activates the drivers for the input signals such as IRQ.
Page 43 Active Address Range Corresponding Chip Select Signal 0x2000 0000 /IDE_PCE1 0x2000 0800 /IDE_PCE2 Table 25: Physical Address Range of the IDE Interface For more information consult your IDE data sheet. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 44 Development Board for phyCORE-PXA255 5.3.2 Compact Flash Interface The PXA255 controller supports two PCMCIA interfaces. The second interface is used on the Development Board as a CompactFlash socket. PLD U7 provides all the control logic to operate the CompactFlash interface.
Page 45 CF card socket. ADDR 0x3001000 PM_5V Table 27: CF Card Control Register 0 Controls the CF card access LED. PM_5V This bit indicates that the 5 V supply voltage is active. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 46 Development Board for phyCORE-PXA255 CF control register 1 is used to set the memory interface. The CF card interface can operate in TruIDE mode if the register bit is set to 0. The PXA255 controller’s PCMCIA interface does not support TruIDE mode.
Page 47 CFPWR Turns on the selected CF card voltage. 5V/3V Selects the CF card voltage; 1 = 5 V, 0 = 3.3 V CF3V Indicates 3.3 V supply active. CF5V Indicates 5 V supply active. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 48 Development Board for phyCORE-PXA255 Control register 5 displays the CF card signals /VS1, /VS2, /BVD1 and /BVD2. /VS1 and /VS2 should be read in order to set the correct CF card supply voltage in CF card control register 4. ADDR...
Page 49 Ethernet Interface 6 Ethernet Interface The Ethernet interface of the phyCORE-PXA255 is supplemented on the Development Board by the Ethernet transformer and the RJ45 connector. phyCORE-PXA255 External PXA255 D0-D31 DATA 10/100Mbps A2-A15 ADDRESS /CS_Ethernet CONTROL ETHERNET IRQ_Ethernet SPI_EEPROM Figure 18: Ethernet Circuitry The Ethernet interface is accessible on the RJ45 socket at X23.
Page 50 Development Board for phyCORE-PXA255 The Ethernet chip’s physical memory area is given in the following table. The address decoder generates the Ethernet /CS at address 0x14000000. In addition an offset of 0x00000300 has to be added. Ethernet Start Address /CS_ETH + OFFSET...
Page 51 2 * USB Host Power Ethernet AC97 Socket Client FF-UART BT-UART Touch Connect Touch Panel Figure 20: USB Host Connector Reset Button GPIO Button MultiMediaCard CompactFlash Card Sound Figure 21: Location of the USB OTG Socket © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 52 Development Board for phyCORE-PXA255 The following table gives an overview of jumpers relevant for configuring the USB interface: Jumper Default Comment This jumper configures the USB controller OTG ID input. Refer to ISP1362 USB-OTG controller data sheet and user’s manual for details.
Page 53 PC. The interface extends to a USB client socket X22 on the Development Board. Expansion Board RESET Button Client 2 * USB Power Host Ethernet AC97 Socket FF-UART BT-UART Touch Connect Touch Panel Figure 22: USB Client Connector © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 55 Hirose connector plug to a ribbon cable connector plug. Furthermore, there is a 2.0 mm universal connector plug on the board at X33, where other display types can be adapted to the PXA255’s LCD port. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 56 Development Board for phyCORE-PXA255 Signal Signal PCLK LCLK FCLK LCD_ENAB 3.3V VCC 3.3V VCC LCD_POS1 LCD_POS2 LCD_POS3 Table 36: LCD Connector at X33 The supply voltage for the TFT display and the inverter can be turned on with the help of a register in control PLD U6. The brightness of the background illumination can be set using the controller’s PWM0...
Page 57 RS-232 Interface The PXA255 controller has four internal UARTS. Three of these are supported in the current version of the phyCORE-PXA255. Two of the interfaces are accessible in the standard RS-232 level over DB-9 sockets at P1 (FF-UART) and P2 (BT-UART).
Page 58 Development Board for phyCORE-PXA255 JTAG Interface Matrix Keyboard GPIO Button Reset Button IDE Interface phyCORE-PXA255 LCD Connectors Inverter Connector Expan. Board Expansion Board connected Touch Underside Connector for PHYTEC Expansion Boards AC97 Connector IR-UART AC97 AC97 AC97 Power BT-UART FF-UART...
Page 59 The FF-UART (Full Feature UART) is a UART with all modem and control signals and a maximum transfer rate of 921.5 kBaud. This interface is used on the phyCORE-PXA255 for communication with the PC. The RS-232 transceiver device is located on the phyCORE module at U1.
Page 60 Development Board for phyCORE-PXA255 10.2 BT-UART The BT-UART has the same properties as the FF-UART, however only the signals BT_RxD, BT_CTC and BT_RTS are supported. The TTL signals RXD and CTS can be separated from the RS-232 transceiver at U42 with Jumper JP2 set to 3+4 and 5+6. The RS-232 transceiver is located on the Development Board.
Page 61 This jumper connects the IR-UART to the RS-232 transceiver. 1 + 2 closed IR_RXD connected to RS-232 transceiver. 3 + 4 BT_RXD connected to RS-232 transceiver. 5 + 6 BT_CTS connected to RS-232 transceiver. Table 39: IR-UART Jumper Configuration © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 63 Development Board. Jumpers JP7 and JP10 must be closed at position 2+3 in order to support galvanic separation, when closed at position 1+2 the CAN interface is powered by the internal 5 V supply from the Development Board. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 64 Development Board for phyCORE-PXA255 Jumper Default Comment This jumper configures the CAN circuitry supply voltage. 1 + 2 CAN supply voltage derived from on-board supply voltage 2 + 3 CAN supply voltage from external source for optical isolation JP10 This jumper configures the CAN circuitry supply voltage.
Page 65 Connection to other AC97 devices such as modems is possible via this socket. Signal Signal VCC (3,3V) VCC (3,3V) /ENA_AC97 /ACRESET SYNC BITCLK SDATA_OUT SDATA_IN0 SDATA_IN1 AC_INT Table 41: AC97 Expansion Socket at X24 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 67 Another functional block of the WM9712L allows for controlling of loudspeakers. A miniature loudspeaker connected to MonoOut is implemented on the Expansion Board. A larger 0.4W loudspeaker is located on the Development Board at X36 and is connected to signals LOUT2 and ROUT2. © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 68 Development Board for phyCORE-PXA255 13 MultiMedia Card The second PCMCIA interface of the PXA255 controller is available on the Expansion Board and supports MultiMedia cards. MultiMedia cards are available as memory devices with capacities of 8 to 256 MByte that can be easily removed by the user. Access to the MMC connector is controlled via MMC-CS1.
Page 69 Reset Button MultiMediaCard GPIO Button D5 D4 D2 D1 CompactFlash Card Figure 34: Expansion Board, Top View Reset Button GPIO Button MultiMediaCard CompactFlash Card D2 D1 D5 D4 Sound Figure 35: Expansion Board, Side View © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 70 Development Board for phyCORE-PXA255 The Expansion Board is connected over two, 2.0 mm, 44-pin flat band cables. The pinout of the Development Board plugs X30 and X31 is given in the following table. Using a customer-specific Expansion Board instead of the standard Expansion Board is also possible given the removable connection via flat band cables.
Page 71 /CF_RDY /CF_RESET /CF_IOIS16 OTG_ID /CF_BVD1 OTG_DP1 /CF_BVD2 OTG_DM1 /CF_LED OTG_VCC /CF_VS1 /CF_VS2 /CF_INPACK /RESIN /OTG_LED /SW_ON AUDIO_P /LED_USR AUDIO_N /LED_PWR MMC_WP2 /MMC_LED MMC_CS1 MMCDET2 MMC_CLK MMCDAT MMC_CMD Table 45: Expansion Board Connector X31 Pinout © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 73 PowerLatch. It is important that the other PowerLatch settings are not changed during a write to these LEDs. Reset Button GPIO Button MultiMediaCard CompactFlash Card Sound Figure 36: Location of Push Buttons and LEDs (Side View) © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 74 Development Board for phyCORE-PXA255 JTAG Interface Matrix Keyboard GPIO Button Reset Button IDE Interface phyCORE-PXA255 LCD Connectors Inverter Connector Expan. Board Expansion Board connected Touch Underside Connector for PHYTEC Expansion Boards AC97 Connector AC97 AC97 AC97 Power BT-UART FF-UART 2 * USB...
Page 75 Matrix Keyboard 16 Matrix Keyboard The phyCORE-PXA255 is populated with a GPIO expander, which can be used for the connection of a matrix keyboard. The signal lines extend to connector X4 and are arranged in columns and rows. The column outputs have an in-line resistance of 33R and the row inputs have an RC combination with R=1 kOhm against VCC and C = 100 nF against GND to prevent a possible signal bounce.
Page 77 GPIO Expansion Board Interface The Development Board also provides a socket for standardized PHYTEC Expansion Boards. All signals except the data, address and control bus of the phyCORE-PXA255 extend from phyCORE connector X18 to the expansion connector X17 in a strict 1:1 arrangement.
Page 78 Development Board for phyCORE-PXA255 Pin Number Signal I/O Comments Pin Row X17A CLKIN Optional external clock input of the processor 2A, 7A, 12A, Ground 0 V 17A, 22A, 27A, 32A, 37A, 42A, 47A, 52A, 57A, 62A, 67A, 72A, GPIO2 I/O Processor I/O port,...
Page 79 I/O LCD frame clock alternative: GPIO74 I/O LCD enable L_BIAS alternative: GPIO77 73A, 74A, I/O LCD data L_DD3, L_DD5 75A, 76A, L_DD6, L_DD8, alternative: GPIO61, GPIO63, GPIO64, 78A, GPIO66, GPIO69, GPIO71, GPIO72 L_DD11, 79A, L_DD13 L_DD14 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 80 Development Board for phyCORE-PXA255 Pin Number Signal I/O Comments Pin row X17B DEV_RES Reset for USB, CAN and Ethernet Device only GPIO_3 I/O Processor I/O port, alternative: interrupt GPIO_1 I/O Processor I/O port, alternative: interrupt 4B, 9B, 14B, Ground 0 V...
Page 81 USB Controller Over Current Inputs Cannel /H_OC2 1 /2 /RESIN I/O /Reset input for reset controller at U9 /RESET_OUT I/O /Reset output of the PXA255 processor NSSP_FRM I/O Network SPI Frame signal, use for CAN Controller alternative: GPIO 82 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 82 Development Board for phyCORE-PXA255 Pin Number Signal I/O Comments Pin row X17C NSSP_CLK I/O Network SPI Clock signal, use for CAN Controller Alternative: GPIO 81 NSSP_TxD I/O Network SPI TxD signal, use for CAN Controller Alternative: GPIO 83 NSSP_RxD I/O Network SPI RxD signal, use for CAN...
Page 83 3-5.0 V OTG_VBUS USB Controller VBUS signal /H_PSW1 USB Controller Power Switch 1 signal /H_PSW2 USB Controller Power Switch 1 signal /RESET Reset output from reset controller /BATT_FAULT Low battery voltage indication © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 84 Development Board for phyCORE-PXA255 Pin Number Signal I/O Comments Pin row X17D /VCC_FAULT Low supply voltage indication PWR_ENAB Power Enable PXA255 BT_CTS CTS Bluetooth UART Alternative: GPIO 44 BT_RXD RXD Bluetooth UART Alternative: GPIO 42 BT_TXD TXD Bluetooth UART Alternative: GPIO 43...
Page 85 FL_DIS Signal to disable internal Flash H_SUSWKUP I/O USB controller /H_SUSWKUP D_SUSWKUP I/O USB controller /D_SUSWKUP OTG_LED I/O USB controller LED signal /INT_RTC Interrupt output RTC Table 46: GPIO Expansion Bus X17 Pin Assignment © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 86 Development Board for phyCORE-PXA255 The pin assignment on the phyCORE-PXA255, in conjunction with the expansion bus (X2) on the Development Board and the patch field on an expansion board, is as follows: phyCORE-PXA255 Development Board Expansion Board Expansion Bus Patch Field...
Page 87 L_DD11 BUS139 BUS107 L_DD13 BUS141 BUS109 L_DD14 BUS142 BUS110 DEV_RESET BUS1 BUS1 GPIO_3 BUS2 BUS2 GPIO_1 BUS4 BUS4 /CS_3 BUS7 BUS7 /CS_5 BUS9 BUS9 BUS10 BUS10 BUS12 BUS12 BUS15 BUS15 BUS17 BUS17 BUS18 BUS18 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 88 Development Board for phyCORE-PXA255 phyCORE-PXA255 Development Board Expansion Board Expansion Bus Patch Field BUS20 BUS20 BUS23 BUS23 BUS25 BUS25 BUS26 BUS26 BUS36 BUS36 BUS39 BUS39 BUS41 BUS41 BUS42 BUS42 DQM_0 BUS52 BUS52 DQM_3 BUS55 BUS55 BUS57 BUS57 BUS58 BUS28 BUS60...
Page 89 IR_TXD GPIO10 GPIO10 IR_RXD GPIO12 GPIO12 FF_IR_DETECT GPIO13 GPIO13 FF_/INVALID GPIO15 GPIO15 /ACRESET GPIO18 GPIO18 SYNC GPIO20 GPIO20 BITCLK GPIO21 GPIO21 SDATA_IN_1 GPIO23 GPIO23 SDATA_IN_0 GPIO26 GPIO26 SDATA_OUT GPIO28 GPIO28 GPIO29 GPIO29 GPIO31 GPIO31 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 90 Development Board for phyCORE-PXA255 phyCORE-PXA255 Development Board Expansion Board Expansion Bus Patch Field /LAN_LED_A /LAN_LED_B LAN_TPI- LAN_TPO- OTG_ID GPIO42 GPIO34 PWM0 GPIO44 GPIO36 PWM1 GPIO45 GPIO37 /TRST GPIO47 GPIO39 H_DP2 GPIO50 GPIO42 H_DM2 GPIO52 GPIO44 MMC_CS_1 GPIO53 GPIO45 MMC_CS_0 GPIO55...
Page 91 USB_N GPIO35 GPIO35 LAN_TPI+ LAN_TPO+ OTG_DP1 GPIO41 GPIO38 OTG_DM1 GPIO43 GPIO40 GPIO46 GPIO41 GPIO48 GPIO43 GPIO49 GPIO46 GPIO51 GPIO48 MMC_CLK GPIO54 GPIO49 MMC_DAT GPIO56 GPIO51 MMC_CMD GPIO57 GPIO54 GPIO_5 GPIO59 GPIO56 GPIO_11 GPIO62 GPIO57 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 92 EGPIO15 EGPIO19 EGPIO20 EGPIO21 EGPIO23 EGPIO26 SSP_EXTCLK GPIO96 GPIO73 SSP_CLK GPIO97 GPIO75 SSP_SFRM FL_DIS H_SUSWKUP D_SUSWKUP OTG_LED /INT_RTC GPIO110 GPIO78 Table 47: Signal Pin Assignment for the phyCORE-PXA255 / Development Board / Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 93 X254. This connector is located on the left side above the phyCORE module. The following table describes the pin assignment for the JTAG interface. Signal Signal VREF /JTAG-RESET JTAG-TDI JTAG-TMS JTAG-TCK JTAG-RTCK JTAG-TDO RESET (System) N.C. N.C. Table 48: JTAG Connector X29 Pinout © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 95 The physical dimensions of the Development Board are represented in Figure 40. PHYTEC is currently working on an enclosure for this Development Board with Expansion Board. The dimensions shown below are subject to change. The maximum height of all components, the inserted phyCORE module and with a display mounted on the PCB is ca.
Page 96 Development Board for phyCORE-PXA255 Figure 41: Physical Dimensions (Expansion Board) Additional specifications: • Dimensions (Development Board): 225 mm x 170 mm • Dimensions (Expansion Board): 35 mm x 150 mm • Weight: approximately 1000 grams • Storage temperature: 0°C to +85°C •...
Page 97 If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee is voided. • Integrating the phyCORE-PXA255 into a Target Application Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module.
Page 99 Component Placement Diagram 21 Component Placement Diagram Figure 42: Component Placement Diagram Development Board (PCB Revision 1220.1) Figure 43: Component Placement Diagram Expansion Board © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 100 Development Board for phyCORE-PXA255 22 Revision History Date Version numbers Changes in this manual 03-Oct.-2004 Manual L-657e_0 First preliminary edition. PCM-990 PCB# 1220.1/1220.2 PCM-985 PCB# 1222.1 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 103 CF LED ........37 IDEIN ........34 CF3V .........39 IDEOE ........34 CF5V .........39 IDEON........34 CFIN..........39 IDEPWR........34 CFOE.........39 IR-UART........54 CFON ........39 ISP1362 ........44 Compact Flash Interface ...36 CompactFlash......36 JP10 ........56, 57 Control PLD ......21 JP2 ........53, 54 © PHYTEC Meßtechnik GmbH 2004 L-657e_0...
Page 104 Development Board for phyCORE-PXA255 JP3..........45 JP5..........45 RDY ..........38 JP6..........45 RDYENA ........38 JP7........56, 57 Removable Jumpers ....13 JP9..........45 RES_POL........38 JTAG......... 86 RESENA ........38 JTAG Interface......86 RJ45...........42 Jumper Layout......13 RS-232........50 LAN91C111......42 Solder Jumpers ......13 LCD...........
Page 105 Suggestions for Improvement Document: Development Board for phyCORE-PXA255 Document number: L-657e_0, Preliminary Edition November 2004 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG...

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Summary of Contents for Phytec phyCORE-PXA255