Sony PCS-G50 Service Manual page 40

command> auto
==== PCS-G50/P Self Diag start! ====
== Count : 1/1 ==
time is 13:15:32
.Read check at an specified area
Bus Opentest ..
.Compare the read value at the header area of each device and the expectation value
Device Read test ..
Testing Audio FPGA (CPU IC 1001).. OK
Testing Video FPGA (DSP IC 1401).. OK
Testing NAZCA (CPU IC 601).. OK
Testing MS Controller (CPU IC 504).. OK
.Read/write check for the register area of each device
Device R/W test ..
Testing VOA (CPU IC 801) ..OK
Testing VOA (CPU IC 801) ..OK
Testing VIA1 (DSP IC 2101) ..OK
Testing VIA1 (DSP IC 2101) ..OK
Testing VIA1 (DSP IC 2101) ..OK
Testing VIA2 (DSP IC 2201) ..OK
Testing VIA2 (DSP IC 2201) ..OK
Testing VIA2 (DSP IC 2201) ..OK
Testing Sysport PLD (CPU IC 302) ..OK
Testing Sysport PLD (CPU IC 302) ..OK
Testing Audio FPGA (CPU IC 1001) ..OK
Testing Audio FPGA (CPU IC 1001) ..OK
Testing Video FPGA (DSP IC 1401) ..OK
Testing Video FPGA (DSP IC 1401) ..OK
Testing NAZCA (CPU IC 601) ..OK
Testing NAZCA (CPU IC 601) ..OK
Testing SIO1 (DSP IC 1101) ..OK
Testing SIO2 (DSP IC 1102) ..OK
Testing MS Controller (CPU IC 504) ..OK
== SH Bus R/W test : OK ==
.USB controller check
-- USB[ CPU/ IC2102 ] Controller Test...
USB Revision ID =
USB Chip ID = 3630
reg error count = 0 / 100
USB Host Controller[ CPU/ IC2102 ]: OK!
.Communication check between each device and DRAM
Testing VIA1(DSP IC2101) DRAM(IC2102)...
Testing VIA2(DSP IC2201) DRAM(IC2202)...
Testing NAZCA(CPU IC601) DRAM(IC602,603)...
Testing VOA (CPU IC801)
.TIDSP check
TI[ DSP ]- checking start ... ... ... ...
TI[ DSP/ IC201 ]- mode pin check( OK )
- EMIFA check( OK )
- download complete( OK )
TI[ DSP/ IC501 ]- mode pin check( OK )
- EMIFA check( OK )
- download complete( OK )
TI[ DSP/ IC801 ]- mode pin check( OK )
- EMIFA check( OK )
- download complete( OK )
TI[ CPU/IC1651 ]- mode pin check( OK )
- EMIFA check( OK )
- download complete( OK )
.Communication check between TIDSP and DRAM
ALL TI[ DSP ] - SDRAM check in progress
- *****************************************
TI[ DSP/ IC201 ]- SDRAM area OK!
TI[ DSP/ IC501 ]- SDRAM area OK!
TI[ DSP/ IC801 ]- SDRAM area OK!
TI[ CPU/IC1651 ]- SDRAM area OK!
4-6
AD-00
11 OK
OK
OK
== OK ==
== OK ==
== OK ==
DRAM(IC802)... == OK ==
DSP/[ IC302, IC303 ]
DSP/[ IC602, IC603 ]
DSP/[ IC902, IC903 ]
CPU/[IC1702, IC1703]
Continues to the
next page
In case of NG, conduct the
following flow.
(Refer to Section 3-1-2.)
No.1
No.2
No.13
No.26
No.10
No.11
No.12
No.23
No.1
No.2
No.13
No.24
No.25
No.26
No.27
No.28
No.29
No.30
No.31
No.7
No.8
No.9
No.6
No.32
PCS-G50/G50P