HOLT ADK-2130mPCIe Technical Manual page 44

5
U2F
A1 M11
GND VCCBRAM
A3 N11
GND VCCBRAM
A5 G10
GND VCCINT
A7 H10
GND VCCINT
A9 J10 C49 C50
GND VCCINT
A19 L10
GND VCCINT
B3 M10
.1uF .1uF
E
GND VCCINT
B5 N10
GND VCCINT
B7
GND
B9 3x .1uF close to pins
GND
B14
GND
C2
GND
C3 H13
GND VCCAUX
C4 J13 C54
GND VCCAUX
C6
GND
C10
.1uF
GND
C19
GND
D3
GND
E3 MGTAVCC1V
GND
F1
GND
F2 C1
GND MGTAVCC
F3 E1
GND MGTAVCC
F18 G9
GND MGTAVCC
G8 H9
GND MGTAVCC
G11
GND C60
H7
D GND .1uF
H8 C65
GND
H11 .1uF
GND
H12
2x .1uF close to pins
GND
J2
GND
J8
GND
J9 B1
GND MGTAVTT
J11 C5
GND MGTAVTT
J12 E2
GND MGTAVTT
J18 G7
GND MGTAVTT
K8
GND
L8 C66 C67
GND
L9 .1uF .1uF
GND
L11
GND
M2
GND 2x .1uF close to pins
M9
GND
M18
GND
N9
GND
N12
GND
R2
C
GND
R18
GND
V2
GND
V5
GND
V8
GND
V12
VCCO3V3
GND
V15
GND
V18
GND
W1
GND
W19
GND
U13
1
OE OUT
XC7A12T-2CPG238
2x1.6mm
100MHZ OSC
Near FPGA pin V1 for minimum distance.
B
10 ohm near Osc module.
LED D6
R41
470
led0 RT1ENA0
D7 RT1MC80
LED
R42 RT2ENA0
470
led1 RT2MC80
MCLK50
LED D8
R43 MTTCLK
470
led2 TTCLK
A
MTRUN0
LED D9
R44 MTPKTRDY0
470
led3 READY0
ACTIVE0
nIRQ0
nMR0
TEST0
5
4
VCCINT_1V
VCCO3V3
C51 C53
+ +
C52
N8
47uF 47uF
VCCO_34
N7
.47uF
VCCO_34
M8
VCCO_34
M7
VCCO_34
47 and 4.7 near perimeter. L7
VCCO_34
K7
VCCAUX_1V8
VCCO_34
J7
VCCO_34
C56
+
C55
C58
47uF C59
4.7uF C57
+
47uF 4.7uF 0.47uF
C62 C63 C64
C61
0.47uF 0.47uF 0.47uF
4.7uF
4.7uF close but outside
FPGA perimeter.
MGTAVTT1V2
.47uF close as possible to pins
47 and 4.7 near perimeter.
C68
4.7uF
4.7uF close but outside
FPGA perimeter.
0.47uF
C69
XC7A12T-2CPG238
R39 10
3 MCLK100M
MEMS OSC 100MHz
DEV0[16:0]
DEV00 DEV10
DEV01 DEV11
DEV02 DEV12
DEV03 RT1ENA1 DEV13
DEV04 RT1MC81 DEV14
DEV05 RT2ENA1 DEV15
DEV06 RT2MC81 DEV16
DEV07 MCLK50 DEV17
DEV08 MTTCLK DEV18
DEV09 TTCLK DEV19
DEV010 MTRUN1 DEV110
DEV011 MTPKTRDY1 DEV111
DEV012 READY1 DEV112
DEV013 ACTIVE1 DEV113
DEV014 nIRQ1 DEV114
DEV015 nMR1 DEV115
DEV016 TEST1 DEV116
4
3
U2D
G3
IO_0_34
G2
IO_L1P_T0_34
G1
IO_L1N_T0_34
H3
IO_L2P_T0_34
H2 CH1INHIBIT1
IO_L2N_T0_34
CH1BCENA1_IN
H1
IO_L3P_T0_DQS_34
J1 CH1BCTRIG1_IN
IO_L3N_T0_DQS_34
K2 CH0BCENA0_IN
MTPKTRDY1
IO_L4P_T0_34
K1 MTPKTRDY0
IO_L4N_T0_34
J3 SPAREINPUT
IO_L5P_T0_34
CH0BCTRIG0_IN
K3
IO_L5N_T0_34
L3 ACTIVE1
IO_L6P_T0_34
L2
IO_L6N_T0_VREF_34
L1 ACTIVE0
IO_L7P_T1_34
M1 RT1MC80
IO_L7N_T1_34
N2 RT2MC81
IO_L8P_T1_34
P2
TEST1
IO_L8N_T1_34
N1 RT1MC81
IO_L9P_T1_DQS_34
P1 TEST0
IO_L9N_T1_DQS_34
M3 RT2MC80
IO_L10P_T1_34
N3 READY0 4
IO_L10N_T1_34
R1 MTTCLK
IO_L11P_T1_SRCC_34
T1 GPIO
IO_L11N_T1_SRCC_34
P3 6
IO_L12P_T1_MRCC_34
R3 TTCLK
IO_L12N_T1_MRCC_34
T3
IO_L13P_T2_MRCC_34
T2 MCLK50 4
IO_L13N_T2_MRCC_34
U1 MCLK100M
IO_L14P_T2_SRCC_34
V1
IO_L14N_T2_SRCC_34
U3 READY1
IO_L15P_T2_DQS_34
U2
led0
IO_L15N_T2_DQS_34
U4 led1
IO_L16P_T2_34
V3 led2
IO_L16N_T2_34
V4 led3
IO_L17P_T2_34
W4 MTRUN0
IO_L17N_T2_34
W3 MTRUN1
IO_L18P_T2_34
W2 CH0BCTRIG0
IO_L18N_T2_34
U6 CH1BCTRIG1
IO_L19P_T3_34
U5 CH0BCENA0
IO_L19N_T3_VREF_34
W6
CH1BCENA1
IO_L20P_T3_34
W5 RT1ENA0
IO_L20N_T3_34
U7 RT1ENA1
IO_L21P_T3_DQS_34
V6 RT2ENA0
IO_L21N_T3_DQS_34
U9 RT2ENA1
IO_L22P_T3_34
U8 nMR0
IO_L22N_T3_34
W9 nMR1
IO_L23P_T3_34
W8
IO_L23N_T3_34
V7
IO_L24P_T3_34
W7 nIRQ0
IO_L24N_T3_34
V9 nIRQ1
IO_25_34
VCCO3V3aux0
DEV1[16:0]
VCCO3V3aux1
VCCINT_1V
VCCAUX_1V8
VCCO3V3
MGTAVCC1V
MGTAVTT1V2
3V3aux
GND
GND
3
2
CHANNEL 0 APOS CH00
CHANNEL 0 ANEG CH01
CH0INHIBIT0 6 1 U9A
74LVC2G14 CHANNEL 0 BPOS CH02
CHANNEL 0 BNEG CH03
4 3
U9B
74LVC2G14 CHANNEL 1 APOS CH10
CHANNEL 1 ANEG CH11
6 1 U10A
74LVC2G14 CHANNEL 1 BPOS CH12
CHANNEL 1BNEG CH13
U11
SPAREINPUT 4 2
74LVC1G14 SC70
3 U10B
74LVC2G14
1 U12A
74LVC2G14
3 U12B
74LVC2G14
R29 10K
R31 10K
R33 10K
R35 10K
VCCO3V3
D4
TPD4E02B04DQAR TPD4E02B04DQAR
GND
CH0[10:0]
CH00 CHANNEL 0 APOS
VCCO3V3aux0
CH01 CHANNEL 0 ANEG
CH02 CHANNEL 0 BPOS
VCCO3V3aux1
CH03 CHANNEL 0 BNEG
VCCINT_1V
CH04 CH0INHIBIT0
VCCAUX_1V8
CH05 CH0BCENA0
CH06 CH0BCTRIG0
VCCO3V3
MGTAVCC1V
MGTAVTT1V2
3V3aux
Title Title Title
Size Size Size
B B B
Date: Date: Date:
2
1
Primary 20 pin conn.
J4
1
2
3
4 Mt1
5
6
Mt Plated
7
8
9
10
11
12
13
14
15
Mt2
16
17 Mt Plated
18
19
20
TP11
GPIO R28
R30 10K 330
R32 10K
R34 10K
R36 10K
TP12
D5
ADC input. 10V R37
Max.
9.1K
ADCINP
R38
1K
R40
ADCINN
0
CH1[10:0]
CH10 CHANNEL 1 APOS
CH11 CHANNEL 1 ANEG
CH12 CHANNEL 1 BPOS
CH13 CHANNEL 1 BNEG
CH14 CH1INHIBIT1
CH15 CH1BCENA1
CH16 CH1BCTRIG1
Holt PCIe-Mini dual MIL-STD 1553 Holt PCIe-Mini dual MIL-STD 1553 Holt PCIe-Mini dual MIL-STD 1553
Document Number Document Number Document Number
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Thursday, January 16, 2020 Thursday, January 16, 2020 Thursday, January 16, 2020 Sheet Sheet Sheet 5 5 5 o f o f o f 5 5 5
1
E
D
C
B
A
R e v R e v R e v
A A A