Adaptec AIC-6915 Programmer's Manual
  1. Manuals
  2. Brands
  3. Adaptec Manuals
  4. Controller
  5. AIC-6915
  6. Programmer's manual
Adaptec AIC-6915 Programmer's Manual

Adaptec AIC-6915 Programmer's Manual

Ethernet lan controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
AIC-6915
Ethernet LAN Controller
Document Title: ABA-1030 DVB Satellite Receiver
Stock Number: 512130-00, Rev. A
Print Spec Number: 497767-00, Rev. AA
Current Date: 10/10/98
Programmer's Manual
Cover-1
R

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the AIC-6915 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Adaptec AIC-6915

Summary of Contents for Adaptec AIC-6915

  • Page 1 AIC-6915 Ethernet LAN Controller Document Title: ABA-1030 DVB Satellite Receiver Stock Number: 512130-00, Rev. A Print Spec Number: 497767-00, Rev. AA Current Date: 10/10/98 Programmer’s Manual Cover-1...
  • Page 2 Adaptec, Inc. 691 South Milpitas Boulevard Milpitas, CA 95035 © 1998, Adaptec, Inc. All rights reserved. Adaptec and the Adaptec logo are registered trademarks of Adaptec, Inc. Printed in Singapore STOCK NO: 512130-00, Rev. A SG 9/98 Document Title: ABA-1030 DVB Satellite Receiver Stock Number: 512130-00, Rev.
  • Page 3 AIC-6915 Ethernet LAN Controller Programmer’s Manual Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Page: Front Matter-i Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 ECN Date: xx/xx/xx...
  • Page 4 Copyright © 1998 Adaptec, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of Adaptec, Inc., 691 South Milpitas Blvd., Milpitas, CA 95035.

  • Page 5: Table Of Contents

    Type 3, 32-bit Addressing Mode (Frame Descriptor) 3-9 Type 4, 32-bit Addressing Mode (Frame Descriptor) 3-9 Transmit Completion Queue Entry 3-10 Document Title: AIC-6915 Ethernet LAN Controller Programmer’s Manual Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x...
  • Page 6 AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI Module Architecture Features 4-1 PCI Block Diagram 4-3 PCI Master Module 4-4 64-bit PCI Bus Master 4-5 Arbitration 4-6 PCI Target Module 4-6 Power Management 4-8 CardBus 4-9 Retry Function 4-9 Response to PCI Commands 4-9...
  • Page 7 Transmit Process 8-16 Transmit Completion Descriptor Queue 8-16 Transmit Completion Descriptor Types 8-17 Transmit Buffer Descriptor Queue 8-17 Document Title: AIC-6915 Ethernet LAN Controller Programmer’s Manual Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98...
  • Page 8 AIC-6915 Ethernet LAN Controller Programmer’s Manual Transmit Buffer Descriptor Types 8-18 Two Transmit Queues 8-20 Transmit Producer-Consumer Model 8-20 Transmit Initialization 8-21 Transmit Handling 8-25 Transmit Completion Interrupt Handling 8-27 AIC-6915 DDK Features 8-29 DDK Development Environment 8-30...
  • Page 9 Figure AIC-6915 Block Diagram 1-5 The AIC-6915 Receive Data Structures 2-2 Transmit Host Communication Data Structure 3-4 PCI Block Diagram 4-3 64-bit PCI Reset Timing 4-5 Data Processing Unit 5-5 AIC-6915 PCI Address Map 7-3 Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev.

  • Page 10: Document Title: Document Title Stock Number: Xxxxxx-Xx Rev

    Document Title: Document Title Stock Number: xxxxxx-xx Rev. x Page: Front Matter-viii Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 ECN Date: xx/xx/xx...
  • Page 11 PCI Command Register 7-6 PCI Status Register 7-7 Device Revision ID Register 7-9 Program Interface Register 7-9 Subclass Register 7-9 Document Title: AIC-6915 Ethernet LAN Controller Programmer’s Manual Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98...
  • Page 12 7-50 TxDescQueueProducerIndex Register 7-40 7-51 TxDescQueueConsumerIndex Register 7-41 7-52 TxDmaStatus1 Register 7-41 Document Title: AIC-6915 Ethernet LAN Controller Programmer’s Manual Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 Page: Front Matter-x ECN Date: xx/xx/xx...
  • Page 13 7-94 NonBkToBkIPG Register 7-75 7-95 ColRetry Register 7-75 7-96 MaxLength Register 7-76 Document Title: AIC-6915 Ethernet LAN Controller Programmer’s Manual Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 Page: Front Matter-xi ECN Date: xx/xx/xx...
  • Page 14 Transmit Frame Processor Register 7-87 7-111 Receive Frame Processor Register 7-87 7-112 FifoAccess Register 7-87 AIC-6915 DDK Features 8-29 Document Title: AIC-6915 Ethernet LAN Controller Programmer’s Manual Stock Number: xxxxxx-xx Rev. x Print Spec Number: xxxxxx-xx Rev. x Current Date: 10/10/98 Page: Front Matter-xii...

  • Page 15: Introduction

    Ethernet NICs (Network Interface Cards). The AIC-6915 integrates all the functions necessary for an Ethernet PCI adapter to directly connect (via a Medium Independent Interface (MII) -based PHY and line transformer) to Category 5 unshielded twisted pair (UTP) or shielded twisted pair (STP).

  • Page 16: Features

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Features General Supports four general purpose I/Os that can be programmed separately as inputs, outputs, open-drain outputs or, interrupt inputs Interface to an external, 8-bit Boot ROM with a maximum size of 256-KByte Supports dynamic system bus (PCI) clock where the network can continue to...

  • Page 17: Internal Buffer Management

    Supports 32- and 64-bit addressing of Host DMA buffers and DMA descriptor queues Big/Little endian support for data and descriptors Special output pin to indicate high-priority PCI request Internal Buffer Management Large, 8 KByte DMA FIFO (default - 4KByte for transmit, 4-KByte for receive) Programmable hardware-controlled transmit FIFO thresholds to prevent underrun of transmit FIFO and enhance overall system performance Unlimited (limited only by the FIFO size) Receive/Transmit frame queueing in the...
  • Page 18 (implemented in the Ethernet control module) and external Memory port from indirect I/O and memory address spaces PCI target latency of 16 clocks maximum for the first target access cycle. The AIC-6915 initiates a cycle retry when an access requires more than 16 clocks to complete...

  • Page 19: Block Diagram

    Block Diagram Figure 1-1 is a block diagram of the AIC-6915. Status Receive Data (8) Station Address Checksum Receive Clock Status RxFrame Control RxDMA Comp BusAccessControl (64 bits) (Master) Status Receive Clock Domain PCI Clock Domain Transmit Clock Domain Figure 1-1. AIC-6915 Block Diagram...

  • Page 20: Modules

    BusAccessControl - Arbitrates master accesses to the PCI bus from internal modules, and accesses the FIFO from the PCI side. SlaveAccess - Drives the REGBUS to access the internal modules when AIC-6915 is accessed from the PCI bus. General Registers - Contains general control and status registers, timers, and interrupt control.

  • Page 21: Receive Architecture

    Receive Architecture Features The host-related Receive Architecture features are Interrupts may be delayed so that only one interrupt is generated when a group of frames is received Choice of shared or separate completion lists for receive and transmit. An optional second completion list can be used for high-priority traffic Two programmable 256-entry or 2048-entry buffer descriptor lists, with optional smaller lists as defined by an “end”...

  • Page 22: Host Data Structures

    The transmit, receive, and completion descriptors are stored in circular queues. With the descriptor queue, the host writes entries into the queue. The AIC-6915 reads from the descriptor queue and writes to the completion queue, which is in turn read by the host.

  • Page 23: Normal Mode

    When the AIC-6915 needs a descriptor, it always reads the next one regardless of the value in the producer pointer. If the valid bit is set, the AIC-6915 uses the descriptor. If not, it waits for the host to place more descriptors in the queue and to write any values to the producer.

  • Page 24: 32-Bit Addressing Mode

    AIC-6915 Ethernet LAN Controller Programmer’s Manual 32-bit Addressing Mode Table 2-1. 64-bit Addressing Mode Table 2-2. Receive Buffer Descriptor (One-size Buffer, 64-bit Addressing) Descriptor Fields: Address - The address of the buffer. LowAddress - Least-significant 32-bits of address. HighAddress - Most-significant 32-bits of address.

  • Page 25: Accepting Frames

    IP header. If the frame is bad, the AIC-6915 does not inform the host of the buffers it used for that frame. Rather, it backs up its internal pointers and reuses those buffers on the next frame. The receive DMA engine transfers the receive data in amounts equal to the RxBurstSize field specified in RxDmaCtrl register.

  • Page 26: Short (Type 0) Completion Entry

    AIC-6915 Ethernet LAN Controller Programmer’s Manual 0 1 Status1 Table 2-4. Basic (Type 1) Completion Descriptor 0 1 Status1 Status2 Table 2-5. Checksum (Type 2) Completion Descriptor 0 1 Status1 Status2 Table 2-6. Full (Type 3) Completion Descriptor 0 1 Status1...
  • Page 27 Table 2-7. Receive Completion Descriptor (Word 0) Bit(s) Status1 field OK - The frame is good. There were no CRC errors, dribble nibble, illegal lengths, or receive code violations. In ISL mode, the ISL and Ethernet checksums must both be valid.
  • Page 28 AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 2-8. Receive Completion Descriptor (Word 1) Bit(s) Status2 field Perfect - destination address matches one of the 16 predefined “perfect” addresses. Hash - hashed destination address matches a bit set in the hash table CRC Error - TRUE if the packet had a CRC error.
  • Page 29 TimeStamp - Time stamp value at the completion of the received frame. The AIC-6915 provides address filters that have an effect on which receive frames are accepted and how they are processed. For more information on address filtering, refer to Address Filtering Registers on page 7-82.

  • Page 31: Transmit Architecture

    There is a “Skip field” defined in front of each descriptor to reserve space for the driver to store information. The “Skip field” size varies from 0 bytes to 128 bytes and is programmed by the driver at initialization time. The AIC-6915 does not read or write to the “Skip field”.
  • Page 32 AIC-6915 Ethernet LAN Controller Programmer’s Manual There are three kinds of interrupts generated by the transmit DMA engine. A “TxDmaDoneInt” is generated when the entire packet is DMA-transferred. A “TxFrameCompleteInterrupt” is generated when an entire packet is transmitted. There are two control bits, DisableTxDmaCompletion and DmaCompletionAfterTransmitComplete defined in the TxDescQueueCtrl and TxFrameControl registers to enable and disable each one of them.
  • Page 33 Transmit Architecture When the amount of packet data in the FIFO exceeds the “Transmit Threshold,” or when the end of packet is already in the FIFO, the “Transmit Frame” state machine signals the MAC to start transmitting the packet. The transmit frame block handles reading packets from the FIFO, MAC interface and FIFO link list management.

  • Page 34: Transmit Data Structure

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Transmit Data Structure Figure 3-1 illustrates the Transmit Data Structure Buffer Descriptors for Hi-Priority Skip Field Frame Header Pkt 1 Buf1 Pkt 1 Buf2 Pkt 1 Buf3 Skip Field Frame Header Pkt 2 Buf1...

  • Page 35: Transmit Register Set

    DMA burst size. Transmit start threshold. DMA priority threshold. The following is a list of transmit registers used during a host to AIC-6915 communication. High-priority queue consumer index. (Written by the AIC-6915, read by driver). High-priority queue producer index. (Written by the driver, read by the AIC-6915).

  • Page 36: Type 0 Transmit Dma Descriptor (32-Bit Addressing Only)

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 3-1. Type 0 Transmit DMA Descriptor (32-bit Addressing Only) ID = 4’b1011 Total Packet Length Reserved ID: 4 bits. This field is used by the software/debugger to identify the start of a descriptor. If a transmit DMA operation does not see a matched ID in this field, it aborts the DMA operation and sets an interrupt status bit.

  • Page 37: End Bit Functionality

    TxFrameCompleteInt is set after complete transmitting the whole frame. None of the two interrupt status bits is set. TxFrameCompleteInt is set after complete transmitting the whole frame. ‘INTR’ ’. The AIC-6915 sets this bit after INTR Transmit Architecture...

  • Page 38: Type 1 (Generic), 32-Bit Addressing Mode (Buffer Descriptor)

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Total Packet Length: This 16-bit field defines the total packet length. If this field is zero, it is ignored and the total packet length is equal to the sum of all the buffers. If this field is nonzero, it is defined as the total packet length.

  • Page 39: Type 3, 32-Bit Addressing Mode (Frame Descriptor)

    Type 3, 32-bit Addressing Mode (Frame Descriptor) This mode is currently not supported in the AIC-6915. Type 4, 32-bit Addressing Mode (Frame Descriptor) Type 4 enables the driver to execute a simple and fast copy of DOS and OS2 data structure (given by the upper layer software as a frame descriptor) to the descriptor queue area.

  • Page 40: Transmit Completion Queue Entry

    Transmit Complete Entry, differentiated by the MSB of the entry. Three bits are defined in the “Type” field because the AIC-6915 always returns a nonzero value in the DMA Complete Entry. Each Transmit Completion Queue Entry can be programmed as either 4 bytes or 8 bytes.

  • Page 41: Transmit Completion Queue Entry Type = Transmit Complete Entry

    If the AIC-6915 is programmed to transmit two words (8 bytes), the second word (bit 63- 32) is the InterruptStatus register content. Table 3-8. Transmit Completion Queue Entry Type = Transmit Complete Entry 29 28 Type Transmit Status Type -3 bit. Always 3’b101 for Transmit Complete Entry.

  • Page 43: Pci Module Architecture

    PCI Module Architecture Features Compliant with PCI Local Bus Specification, Revision 2.1 Compliant with Intel PCI Bus Power Management Interface Specification Rev 1.00 and Microsoft Device Class Power Management Reference Specification (OnNow) PC 97 ready. Implements all hardware features required by Microsoft’s PC 97 design specification Supports 3.3V and 5.0V PCI signaling Direct pin out connection to PCI 32/64-bit bus interface...
  • Page 44 (implemented in the Ethernet control module) and external Memory port from I/O (indirect) and memory address space. PCI target latency of 16 clocks maximum for the first target access cycle (revision 2.1 support). The AIC-6915 initiates a cycle retry when an access requires more than 16 clocks to complete.

  • Page 45: Pci Block Diagram

    PCI Block Diagram Figure 4-1 is a PCI block diagram. PCI_PADS PCI_TOP BUFOUTFLOPS/OUTFLOPS PCIMST Pcimaster Logic Bus Access Control Data Fifo Figure 4-1. PCI Block Diagram PCI Module PCITGT EEPROMCNTL TGTDPU Datapath Logic TGTCTL control logic BOOTROMCTL DECODER Memory Port Address Decoder Slave Access Ctl PCI Module Architecture...

  • Page 46: Pci Master Module

    DMA transfer even if a parity error is detected. The software driver can request the AIC-6915 to stop the DMA transfer when a parity error is detected and suspend any other DMA operations until the error is serviced.

  • Page 47: 64-Bit Pci Bus Master

    64-bit PCI Bus Master The AIC-6915 supports a 64-bit PCI bus master and performs 64-bit data transfers with a 64-bit target. If the responding target is a 32-bit device, the lower 32-bit of address bus is used. signal is used to determine whether the system supports a 64-bit data path. A REQ64_ pull-up resistor on the motherboard places the PCI bus in 32-bit mode by default.

  • Page 48: Arbitration

    The AIC-6915 uses the expansion ROM base address to request from the system to allocate 256 KBytes of memory space to access an External ROM. When the AIC-6915 detects a PCI cycle which is addressed to it, it checks the command to verify that it can respond, then asserts...
  • Page 49 The target does not support data bursts. Rather it disconnects after the first Data phase. In addition, the AIC-6915 does not support 64-bit target mode data transfers. Two locations in I/O space are used as Data (IndirectIoDataPort) and Address (IndirectIoAddress) registers.

  • Page 50: Power Management

    D3 indicates the “Off” state, and D1 and D2 represent power managed states. In the AIC-6915, three states are supported. D0 and D3 are required states and D2 is an optional state. Table 4-1 shows the states supported by the AIC-6915.

  • Page 51: Cardbus

    32768 PCI clock cycles. Response to PCI Commands The AIC-6915 does not contain cache memory, and the Memory Interface bus gains no special efficiency from cacheline-size bursts, so the AIC-6915’s PCI target responds to the cache-oriented memory space commands (Memory Read Multiple, Memory Read Line, Memory Write and Invalidate) as if they were simple Memory Read or Memory Write commands.

  • Page 52: Target Response To Pci Commands

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 4-2 lists all 16 PCI commands and the corresponding AIC-6915 response. Table 4-2. Target Response to PCI Commands CBE[3:0]_ Command 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100...

  • Page 53: Configuration Address Space

    AIC-6915 indicates a disconnect and only accepts the first Data phase. I/O Address Space (Direct Access) The AIC-6915 uses Base Address 1 to request an allocation of a 256-byte I/O space block and supports only read/write operation to the 256-byte registers, including the IndirectIoDataPort and IndirectIoAddress registers for indirect I/O accesses.

  • Page 54: Expansion Rom Address Space

    The AIC-6915 does not support writes to expansion ROM space. Memory Address Space The AIC-6915 uses Base Address 0 to request an allocation of a 512-KBytes memory space block. are excluded from the address decode and defaults to a word-aligned address.

  • Page 55: Perr

    The Bus Command and Byte Enable bits are multiplexed on the same PCI pins. During the address phase of a transaction, CBE[3:0]_ to be performed during the transaction. Table 4-3 describes how the AIC-6915 responds to different commands. Table 4-3. Address Phase CBE[3:0] Values...

  • Page 56: Illegal Behavior

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Illegal Behavior As a target, when the AIC-6915 accepts a cycle (I/O, memory, configuration) which is addressed to it and drives under any of the following conditions: The combination of AIC-6915 aborts the cycle and sets the...

  • Page 57: Frame Processor Architecture

    Frame Processor Architecture Features Calculate the TCP and UDP checksum Decode frame type (TCP, UDP, ARP, RARP, IPX, Wake-up, VLAN 802.1q, Ipv4, Ipv6, ICMP, Ethernet 2, IEEE 802/803) Process Ethernet 2, 802, IPv4, IPv6, TCP and UDP headers Process receive data on-the-fly. The maximum receive buffer requirement is 8-bytes Same architecture for both transmit and receive Ease of implementation, simple decoding logic, no pipeline, fixed instruction format, simple commands...

  • Page 58: Wake-Up Mode

    AIC-6915 Ethernet LAN Controller Programmer’s Manual LC= 0, 1 or 2, and E Read/Write instruction is executed and the Input IOR Note: LOCK The loop counter is decremented by 2 every clock cycle if E is asserted. The loop counter stops when reaching its terminal count of zero.

  • Page 59: Gfp Address Space

    GFP Address Space A total of 256 address locations can be accessed by the GFP executing Read/Write instructions. The target address is presented in the B instruction. When executing a read or write instruction, the GFP asserts G and drives G [7:0], then waits for G The total address space is divided in two.

  • Page 60: External Registers

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 5-1. Status/Control Register (Continued) StopTxDma - If set, indicates the transmit DMA engine must freeze its operation and wait for software intervention VlanFrame - If set, indicates a VLAN 802.1q frame DiscardFrame - If set, indicates the frame being processed must be discarded (transmit...

  • Page 61: Block Diagram

    Block Diagram Figure 5-1 is a block diagram of the Data Processing Unit. Frame Data Counter WR1 WR2 WR3 WR4 8 Input Mux Mask Control Input1 WR1[31:0] WR2[15:0] Figure 5-1. Data Processing Unit DataValid 8 Input Mux Barrel Shifter Mask Control Input2 Simple ALU: Adder,...

  • Page 62: Instruction Formats

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Instruction Formats Table 5-2 describes the Instruction Formats. Name Bit Number Opcode 0 Opcode 1 Opcode 2 Opcode 3 Opcode 4 Opcode 5 Opcode 6 Opcode 7 Opcode 8 Opcode 9 Table 5-2. Instruction Formats...
  • Page 63 Table 5-2. Instruction Formats (Continued) Name Bit Number Opcode A CheckIpv6NextHeader - Special instruction for checking the Next Header field. The GFP recognizes 8 types of extension headers implemented in hardware, identified by the following Next Header identification number: TcpProtocolId UdpProtocolId HopByHopProtocolId DestinationProtocolId...
  • Page 64 AIC-6915 Ethernet LAN Controller Programmer’s Manual Name Bit Number Opcode E Opcode F ExcOnClock ReqNextData LoadWR1 LoadWR2 LoadWR3 LoadWR4 LoadLC BarrelShifterCtrl MaskCtrl MaskSel MuxSelInput2 [16:14] Table 5-2. Instruction Formats (Continued) Description Return - Return to main program. When branching from the main program, the next instruction pointer value of the main program is saved in a special register.
  • Page 65 Table 5-2. Instruction Formats (Continued) Name Bit Number MuxSelInput1 [29:17] Controls the 8 input mux operation at ALU input 1 ‘0’ - Data ‘1’ - WR1[15:0] ‘2’ - WR2 ‘3’ - WR3 ‘4’ - Status[31:16] ‘5’ - Status[15:0] ‘6’ - FrameCnt ‘7’...

  • Page 67: Aic-6915 Internal Registers Summary

    AIC-6915 Internal Registers Summary For the following registers, the ‘Byte Address’ indicates each registers location in memory space given as a byte offset address from the start of the memory space dedicated for internal registers - 0x50000h. PCI Configuration Header Registers Summary The PCI configuration registers are mapped to Memory Base Address+0x50000 in memory space, 0x00 in configuration spaces and address 0x00 in I/O space.

  • Page 68: Aic-6915 Functional Registers Summary

    AIC-6915 Ethernet LAN Controller Programmer’s Manual AIC-6915 Functional Registers Summary Mapped to address range 0x50040-0x500FF in memory space, address 0x40-0xFF in configuration space and address 0x40-0xFF in I/O space. These registers are read/write and can be accessed using Memory, I/O, and Configuration commands.
  • Page 69 Table 6-2. AIC-6915 Functional Registers Summary (Continued) Byte Offset (Hex) Register Name 00B4 CompletionQueueHighAddr 00B8 TxCompletionQueueCtrl 00BC RxCompletionQueue1Ctrl 00C0 RxCompletionQueue2Ctrl 00C4 CompletionQueueConsumerIndex 00C8 CompletionQueueProducerIndex 00CC RxHiPrCompletionPtrs 00D0 RxDmaCtrl 00D4 RxDescQueue1Ctrl 00D8 RxDescQueue2Ctrl 00DC RxDescQueueHighAddress 00E0 RxDescQueue1LowAddress 00E4 RxDescQueue2LowAddress 00E8 RxDescQueue1Ptrs...

  • Page 70: Additional Pci Registers Summary

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Additional PCI Registers Summary Mapped to address range 0x50FFF-0x50100 in Memory space. These registers can be accessed using memory or indirect I/O commands. Table 6-3. AIC-6915 Additional PCI Registers Summary Byte Offset (Hex) Register Name...
  • Page 71 Table 6-4. AIC-6915 Additional Ethernet Registers Summary (Continued) Byte Offset (Hex) Register Name 500C NonBkToBkIPG 5010 ColRetry 5014 MaxLength 5018 TxNibbleCnt 501C TxByteCnt 5020 ReTxCnt 5024 RandomNumGen 5028 MskRandomNum 502C-5033 5034 TotalTxCnt 5040 RxByteCnt 5060 TxPauseTimer 5064 VLANType 5070 MiiStatus...

  • Page 73: Register Descriptions

    Register Descriptions Overview This section includes all the registers required for controlling, programming, and operating the AIC-6915. All registers throughout this section subscribe to the following format. These bits or fields are under software control. They may be programmed by software to initialize the controller or to optimize performance.

  • Page 74: Aic-6915 Address Space

    AIC-6915 Ethernet LAN Controller Programmer’s Manual AIC-6915 Address Space A device on a PCI bus can be accessed using different PCI command types. The AIC-6915 can be accessed using Memory, I/O and Configuration commands. The 512-KByte address space is mapped to a base address defined by the operating system at boot time.

  • Page 75: Aic-6915 Pci Address Map

    0x50000 External registers (16K words (64KBytes)) (PCI clock domain) 0x40000 (E)EPROM R/W (64KByte words (256KBytes)) (PCI clock domain) 0x00000 Figure 7-1. AIC-6915 PCI Address Map Register Descriptions 64K Internal Registers Address Map 0xFFFF Reserved 0xE000 Ethernet FIFO Access 0xC000 Rx Frame Processor...

  • Page 76: Terminology

    Reading any other byte in a byte or halfword operation does not affect the register. When the AIC-6915 activates a function as a result of writing to a register, the activation takes place (usually) when writing the most-significant-byte of the register.

  • Page 77: Pci Registers

    PCI Registers PCI Configuration Header Registers At the deassertion edge of the PCI reset, the AIC-6915 starts reading the serial EPROM. At the same time, the BR_A1 input is sampled. If the board has a pull-up on this pin, the...
  • Page 78 SERRESPEN: System Error Response Enable. When both SERRESPEN and PERRESPEN are set, the output PCI_SERR_ can be asserted. As a target, the AIC-6915 only asserts PCI_SERR_ for detected address parity errors. SERRESPEN is cleared during and after assertion of PCI_PCIRST_.
  • Page 79 PCI_PCIRST_ or by a write to the STATUS register with bit 13 (=1). RTA: Received Target Abort is set when the AIC-6915, as a PCI bus master, generates a transaction terminated with Target-Abort indication. RTA is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 28 (=1).
  • Page 80 STA is set inactive during and after assertion of PCI_PCIRST_ or by a write to the STATUS register with bit 11 (=1). The AIC-6915 indicates target-abort for the following conditions: Illegal Overlap.

  • Page 81: Device Revision Id Register

    Value PROGINFC[7:0]: The Program Interface register value identifies the specific register-level programming interface the agent supports. The PROGINFC for the first version of the AIC-6915 is identified as 00h. PCI Subclass Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Ah Table 7-9.

  • Page 82: Baseclass Register

    BASECLASS[7:0]: The BaseClass register identifies which base class the PCI device has been assigned to. The BASECLASS for the first version of the AIC-6915 is identified as 02h (Network controller). This value can be changed to a value read from an external serial EEPROM if the BR_A1 pin is ‘1’...

  • Page 83: Header Type Register

    Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Eh Table 7-13. Header Type Register Reset Bit(s) Value HDRTYPE[7]: The AIC-6915 is a single function device HDRTYPE[6:0]: Always read 0. BIST (Built-in Self Test) Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 0Fh...

  • Page 84: High Base Address 0 Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI HighBASEADR0 (Base Address 0) Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 14h - 17h Note: When an access is made to an address that is mapped and enabled in both the BASEADR0 and EXROMCTL registers, the PCI responds with a target abort.

  • Page 85: Subsystemvendor Id Register

    PCI controller has been designed by another vendor and has another Vendors ID. The default value is the Adaptec Vendor ID number, 9004h. This value can be changed to a value read from an external serial EEPROM if BR_A1 pin is ‘1’...

  • Page 86: Expansion Rom Control Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Reset Bit(s) Value 31:18 17:11 10:1 PCI CapPtr (Capabilities List Pointer) Register Type: R/W Internal Registers Subgroup: PCI Configuration Header Byte Address: 34h Reset Bit(s) Value 50’h PCI INTLINSEL (Interrupt Line Select) Register Type: R/W...

  • Page 87: Interrupt Pin Select Register

    EEPROM if BR_A1 pin is asserted when PCI_PCIRST_ is deasserted. This feature enables the integration of multiple AIC-6915 devices on the same PCI card (as a multiport Ethernet NIC) and treats the card as one PCI device with multiple functions having different interrupt lines.

  • Page 88: Maximum Latency Register

    30MByte/Sec = 64 / (0.48usec+MaxLat) MaxLat = (64 / 30) - 0.48 = 1.65333usec =~ 1.50 usec The AIC-6915's MAXLAT register value is 6h, which is 1.5usec/0.25usec. Note: For smaller burst sizes or higher required data transfer rates this number has to change.

  • Page 89: Pci Functional Registers Definition

    ‘011’ - 3 PCI clocks All other combinations are reserved. StopMWrOnCacheLineDis: When this bit is cleared, the AIC-6915 stops any memory write on a cacheline boundary if the remaining number of data transfers is more than the cacheline size. A memory write and invalidate cycle follows.
  • Page 90 MASTEREN is set (PCI Command register). ISPACEEN or MSPACEEN is set (PCI Command register). StopOnCachelineEn: When set, the AIC-6915 stops any memory write or memory write and invalidate on a cacheline. Otherwise it allows the target to control cycle termination.
  • Page 91 Header register space which remains unchanged). The reset pulse is transferred to the other clock domain and remains asserted until the entire AIC-6915 is initialized. As long as the initialization process takes place (no more than 1 other clock period + 4 PCLK periods) the PCI Target does not respond to any PCI cycles.

  • Page 92: Baccontrol Register

    PreferRxDmaReq is also cleared, they have equal (round-robin) priority. Note: The AIC-6915 implements an internal dynamically changing control signal that can force PreferTxDmaReq to ‘1’. This control signal is active when the transmit data falls bellow a programmable threshold and there is a danger of FIFO underrun.

  • Page 93: Pci Monitor1 Register

    PCIC 15:0 PCISlaveBusUtilization: Provides a count of the total number of PCI clock cycles the AIC-6915 asserts PCI_DEVSEL_ as an active PCI slave, measured from the time the software driver resets the register. The count is presented in PCIC...

  • Page 94: Pci Monitor2 Register

    Description/Function PCIMasterBusUtilization: Provides a count of the total number of PCI clock cycles that the AIC-6915 asserts PCI_FRAME_ as an active PCI master, measured from the time the software driver resets the register. The count is presented in; 1 unit=64PCIClkCycles. The...

  • Page 95: Power Management Control Status Register

    Table 7-32. Power Management Control Status Register Reset Bit(s) Value 31:29 PMData: This function is not implemented. The AIC-6915 does not provide information about the power it consumes. 23:16 Reserved: Always read as 0. PmeStatus: This bit is set when the function would normally assert the PME_ signal independent of the state of the P this bit clears it and causes the function to stop asserting a PME_.

  • Page 96: Pme Event Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual PME Event Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 58h- 5Bh Reset Bit(s) Value 31:6 Serial EEPROMControlStatus Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 60h - 63h...

  • Page 97: Eeprom Memory Definition

    MAC address [7:0] --> MAC Addr Byte 1 MAC address [7:0] --> MAC Addr Byte 0 (MSB) Minimum Grant [7:0] Maximum Latency [7:0] 23-124 Reserved Adaptec Standard Format Checksum [7:0] Checksum [15:8] Register Descriptions Value 08 = 62011/TX Rev. 0 09 = 62011/TX Rev. 1...

  • Page 98: Pcicompliancetesting Register

    Description/Function Reserved IndirectIoAddress: Points to a word (4-byte) location in the AIC-6915 512-KByte address space. When an external PCI Master starts a legal access to the Indirect I/O Data Port register (IndirectIoDataPort), the PCI target uses the IndirectIoAddress for addressing the requested register.

  • Page 99: Ethernet Registers

    Ethernet Registers The following registers are accessible from PCI configuration, memory, and direct I/O space. They are all synchronized to the Ethernet Transmit clock. General Ethernet Functional Registers GeneralEthernetCtrl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 70h - 73h Table 7-39.

  • Page 100: Timerscontrol Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual TimersControl Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 74h - 77h Reset Bit(s) value 23:16 7-28 Table 7-40. TimersControl Register Description/Function EarlyRxQ1IntDelayDisable: When set, the interrupt masking timer has no effect on EarlyRxQ1Int.
  • Page 101 DMA transfer of a ‘small’ frame, then R asserts the external PCI interrupt line. When S reset, the AIC-6915 treats all received frames the same. It does not assert the external interrupt line if the interrupt masking timer is active.

  • Page 102: Currenttime Register

    ‘0’. When the software driver writes a ‘01’ or ‘11’ to I , the AIC-6915 loads the interrupt masking timer and prevents the interrupt status bits T from causing a PCI interrupt for a period defined by IntMaskPeriod.

  • Page 103: Pci Status Register

    InterruptStatus Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 80h - 83h This register stores the interrupt vector which indicates the interrupt source. Some of the bits in the register are cleared on a read, while others must be cleared at the source.
  • Page 104 ‘1’. RxQ1LowBuffersInt: Indicates a shortage of receive buffers in receive buffer descriptor queue 1. The bit is set when the AIC-6915 tries to fetch a buffer descriptor and the number of buffers available in the queue is less than a programmable threshold as defined in the register.
  • Page 105 RxQ2LowBuffersInt: Indicates a shortage of receive buffers in the receive buffer descriptors queue 2. The bit is set when the AIC-6915 tries to fetch a buffer descriptor and the number of buffers available in the queue is less than a programmable threshold as defined in the RxDmaCtrl register.

  • Page 106: Shadowinterruptstatus Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual ShadowInterruptStatus Register Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 84h - 87h This register is used for reading the Interrupt Status register in read-only mode. In this mode the interrupt status bits that are defined as ‘cleared by read’ are not affected.

  • Page 107: Pcideviceconfig Register

    InterruptEn Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 88h - 8Bh Specifies if the corresponding bit in I an external PCI interrupt. The PCI interrupt bit must be enabled in the PCID register. EVICE ONFIG Table 7-44. InterruptEn Register Reset Bit(s) Value...

  • Page 108: Gpio Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual GPIO Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 8C - 8Fh The GPIO register provides for host software control of the GPIO[3:0] pins. Reset Bit(s) Value 31:28 27:24 1111 23:20...

  • Page 109: Transmit Registers

    TxDescQueue64bitAddr: If set to a ‘1’, the transmit buffer descriptor queue contains a 64-bit address. The AIC-6915 PCI master must then use the 64-bit addressing mode to access the queue.
  • Page 110 ‘001’ - Basic buffer descriptor, 32-bit addressing. ‘010’ - Basic buffer descriptor, 64-bit addressing. ‘011’ - Special netware frame descriptor with 32-bit addressing. The AIC-6915 builds the Ethernet media header. This type has 4 subtypes associated with it. ‘100’ - Special DOS/OS2 Frame descriptor with 32-bit addressing.

  • Page 111: Hiprtxdescqueuebaseaddress Register

    HiPrTxDescQueueBaseAddr Register Type: R/W Internal Registers Subgroup: Ethernet Functional Registers Byte Address: 94h - 97h Table 7-47. HiPrTxDescQueueBaseAddress Register Reset Bit(s) Value 31:8 HighPriorityTxDescQueueBaseAddress[31:8]: When written with a nonzero value, this field indicates the starting address of the queue in host memory. It is written by the software driver during device initialization.

  • Page 112: Txdescqueuehighaddr Register

    Reserved: Always read as 0. HiPrTxProducerIndex Written by the software driver and read by the AIC-6915. When the software driver wants to transmit a frame, it adds the frame buffer descriptor to the low-priority queue, then updates the Producer Index to point to the next empty location in the queue.

  • Page 113: Txdescqueueconsumerindex Register

    The software driver can write this field only if T disabled and the AIC-6915 cannot continue on to fetch the next descriptor. The producer and consumer indices point to a doubleword (8-byte) address in the queue.

  • Page 114: Txdmastatus2 Register

    “0” to these bits. DmaCompletion After Transmit Complete: If this bit is cleared the AIC-6915 does not set the interrupt status bit . If the bit is set, the AIC-6915 DMA- RAME OMPLETE transfers a completion descriptor after completely transferring the entire frame.

  • Page 115: Completion Queue Registers

    Otherwise, writes to the index are disabled. When the bit is cleared the queue is disabled and the AIC-6915 cannot add entries to the queue. TxCompletionSize: When this bit is set, each transmit completion descriptor size is 8-bytes, which makes the entire completion queue 8-KBytes.
  • Page 116 256-byte boundary. RxCompletionQ1_64bitAddress: The bit indicates if Receive Completion Queue 1 is located in 64-bit address space. If so, the AIC-6915 PCI master must use 64-bit addressing mode to access the queue. RxCompletionQ1ProducerWe: When this bit is set, the software driver is able to write the receive completion queue producer index.

  • Page 117: Rxcompletionqueue2Ctrl Register

    The starting address must be aligned to a 256-byte boundary. RxCompletionQ2_64bitAddress: This bit indicates if Receive Completion queue 1 is located in 64-bit address space. If so, the AIC-6915 PCI Master must use 64-bit addressing mode to access the queue. RxCompletionQ2ProducerWe: When this bit is set, the software driver is able to write the receive completion queue producer index.

  • Page 118: Completionqueueconsumerindex Register

    Reserved: Always read and write 0. TxCompletionConsumerIndex: Written by the software driver and read by the AIC-6915. The software driver increments or writes a new index to free space in the queue. RxCompletionQ1ThresholdMode: This bit indicates when RxCompletionQueue1Int is asserted. In the default state (‘0’) the interrupt is asserted if the number of empty entries in the queue is less than or equal to a programmable threshold.

  • Page 119: Completionqueueproducerindex Register

    Reserved: Always read and written as zero. 25:16 TxCompletionProducerIndex: Written by the AIC-6915 and read by the host driver. The AIC-6915 increments the index by 1 whenever a completion descriptor is successfully DMA-transferred to the transmit (or shared) completion list in host memory. The software driver writes this field only if TxCompletionProducerWe is set, which also disables the completion list.

  • Page 120: Receive Registers

    25:24 7-48 Description/Function RxCompletionQ2ConsumerIndex: Written by software driver and read by the AIC-6915. The software driver increments or writes a new index to free space in the queue. Table 7-62. RxDmaCtrl Register Description/Function RxReportBadFrames: If set, the AIC-6915 reports the status for rejected frames to the host, although it reuses the buffers for the next frame.
  • Page 121 Table 7-62. RxDmaCtrl Register (Continued) Reset Bit(s) Value 22:20 RxDmaQueueMode[2:0]: This field determines how to select the DMA buffer descriptor queue. The encoding is as follows: ‘000’ - Disable buffer descriptor queue 2. DMA all (good) packets to buffers taken from queue 1. ‘001’...

  • Page 122: Rxdescqueue1Ctrl Register

    RxPrefetchDescriptorsMode: Setting this bit places the AIC-6915 in Prefetch mode. The AIC-6915 does not wait for the producer to be updated before fetching a buffer descriptor. When it needs a descriptor, it always reads the next one. If the Valid bit in the descriptor is set, the AIC-6915 uses the descriptor.
  • Page 123 AIC-6915 to automatically wrap to the start of the queue when fetching the next entry. The AIC-6915 still wraps after 256 or 2048 entries even if This control bit is used for both descriptor queues.

  • Page 124: Rxdescqueue2Ctrl Register

    32-bit address of the first Receive Buffer Descriptor Queue. The lower 8 bits of address must be 0. This register is written by host driver during initialization and read by the AIC-6915 during a receive DMA operation.

  • Page 125: Rxdescqueue2Lowaddress Register

    32-bit address of the first Receive Buffer Descriptor Queue. The lower 8 bits of the address must be 0. This field is written by host driver during initialization and read by the AIC-6915 during a receive DMA operation.

  • Page 126: Rxdescqueue2Ptrs Register

    AIC-6915. The software driver should use the E the receive completion descriptor rather that this value to determine which buffer the AIC-6915 has used because if the AIC-6915 receives a bad frame, it reverts the consumer back to the beginning of the frame to reuse the buffers.
  • Page 127 Address filtering, which is controlled by the R various address filtering memories, determines which frames are accepted by the AIC-6915 and passed to the driver. The frame’s destination address is compared against the following three criteria. If the address matches any of these criteria, the frame is accepted.

  • Page 128: Rxaddressfilteringctrl Register

    Note: Any wake-up mode other than 00 disables normal receive operation. VlanMode[1:0]: ‘00’ - VLAN mode disabled. ‘01’ - VLAN mode enabled. The AIC-6915 does not strip the VLAN tag from the frame. ‘10’ - VLAN mode enabled. The AIC-6915 strips the VLAN tag and identifier from the frame.
  • Page 129 SRAM, then DMA transfers the frame if there is not a match. ‘11’ - In VLAN mode, The AIC-6915 accepts frames that match the first perfect address, or whose VLAN ID matches one of the preprogrammed VLAN IDs and whose address matches one of the other 15 perfect addresses.

  • Page 130: Rxframetestout Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual RxFrameTestOut Register Type: R Internal Registers Subgroup: Ethernet Functional Registers Byte Address: F8h- FBh Reset Bit(s) Value 31:24 23:16 15:12 11:8 7-58 Table 7-72. RxFrameTestOut Register Description/Function Reserved: Always read as 0. TestRxFrame: If TestSel[2:0] = 0: TestRxFrame = status0; (default) else If TestSel[2:0] = 1: TestRxFrame = status1;...

  • Page 131: Pci Diagnostic Registers

    Internal Registers Subgroup: PCI Extra Registers Byte Address: 0100h - 0103h This register is for diagnostic purposes only. When the AIC-6915 responds with a target abort, the software driver can determine the reason by reading this register. Table 7-73. PCITargetStatus Register...

  • Page 132: Pcimasterstatus1 Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual PCIMasterStatus1 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0104h - 0107h This register is used for diagnostic purposes to read the internal status of a DMA operation. Reset Bit(s) Value...

  • Page 133: Pcimasterstatus2 Register

    LowHostAddr[31:0]: The Low Host address register contains the low (32-bit) word of the system memory byte address of the data being transferred to or from the AIC-6915 as an active bus master. This register is implemented as a counter that counts up by one for each byte transferred between the device and system memory.

  • Page 134: Bacdmadiagnostic1 Register

    FIFOs when the AIC-6915 is an active bus master. The PCITransferCount field functions as a counter that decrements by one each time a byte is transferred between the PCI master and the FIFOs.

  • Page 135: Bacdmadiagnostic2 Register

    BacDmaDiagnostic2 Register Type: R Internal Registers Subgroup: PCI Extra Registers Byte Address: 0118h - 011Bh This register provides information about the current DMA transfer and is used for diagnostic purposes only. All values in the register are synchronized to the Ethernet clock.

  • Page 136: Bacdmadiagnostic3 Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual BacDmaDiagnostic3 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 011Ch - 011Fh Reset Bit(s) Value 31:25 11:0 7-64 Table 7-80. BACDMADiagnostic3 Register Description/Function Reserved: Always read as 0. IllegalDmaReq: This bit is set during a receive DMA request when the host address is not aligned on a (32-bit) word boundary.

  • Page 137: Macaddr1 Register

    Bit(s) Value 31:0 MacAddr[31:0]: The MAC address of the AIC-6915 is read from the external serial EPROM and loaded in to the M software driver can overwrite the value by writing to this register. NIC’s MAC Addr Byte 5 --> MacAddr[7:0] (LSB) NIC’s MAC Addr Byte 4 -->...

  • Page 138: Pci Cardbus Registers

    PCI CardBus Registers The following registers are defined in the CardBus PC Card Electrical Specification. Their implementation in the AIC-6915 is described here. For more detailed information on the meaning of these bits see the PC Card specification. The registers are accessible from PCI memory and indirect I/O space. They are all synchronized to the PCI clock.

  • Page 139: Functioneventmask Register

    GWake: Always 0. The AIC-6915 does not support wakeup on CardBus as it requires an external power source. BVD[2:1]: Always 0 x 3 (11b). The card containing the AIC-6915 is not expected to have batteries, so the battery is considered “operational”.

  • Page 140: Forcefunction Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual ForceFunction Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 013Ch - 013Fh Setting a bit here also sets a bit in the FunctionPresentState register. Since only the interrupt function is supported, only bit 15 is implemented.

  • Page 141: Additional Ethernet Registers

    ‘31’ which provides the ‘MiiBusy’ status. When the software driver accesses the port and the Serial MII Management port is idle, the AIC-6915 sets the MiiBusy bit and starts an access to the appropriate external physical device. When the access is completed, the AIC-6915 resets the Status bit.

  • Page 142: Testmode Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual TestMode Register (TBD) Type: R/W Internal Registers Subgroup: Ethernet Extra Registers Byte Address: 4000h - 4003h This register controls test mode of the chip. Reset Bit(s) Value 31:9 RxFrameProcessorCtrl Register Type: R/W Internal Registers Subgroup: Ethernet Extra Registers Byte Address: 4004h - 4007h Table 7-89.

  • Page 143: Mac Control Registers

    MAC Control Registers MacConfig1 Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5000h - 5003h Table 7-91. MacConfig1 Register Reset Bit(s) Value 31:16 Reserved: Always read as 0. SoftRst: Software reset to internal MAC logic. This bit has no effect on any configuration register state.
  • Page 144 CRCEN in the first buffer descriptor. When the bit is cleared software is responsible for providing a minimum frame size of 60 bytes and request the AIC-6915 to add the 4-bytes CRC, or provide a complete minimum frame CRC.

  • Page 145: Macconfig2 Register

    A VLAN frame is detected when the VLAN type matches the value contained in the VLAN Type register. Note: If the AIC-6915 is required to calculate and add the CRC, then the minimum frame size is 64 for non-VLAN frames, and 68 for a VLAN type frames.

  • Page 146: Bktobkipg Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual Reset Bit(s) Value For proper operation, the internal MAC must be reset after enabling any of the configuration bits in this register by setting bit 15 (M setting the T and R internal MAC. Setting bit 15 only resets the internal MAC and has no effect on any of the bits in this register.

  • Page 147: Nonbktobkipg Register

    NonBkToBkIPG Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 500Ch- 500Fh Table 7-94. NonBkToBkIPG Register Reset Bit(s) Value 31:15 Reserved: Always reads 0. 14:8 IPGR1: For a non back-to-back transmit operation, a two-part deferral algorithm is implemented. IPGR1 is part 1 and IPGR2 is part 2.

  • Page 148: Maxlength Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual MaxLength Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5014h - 5017h Reset Bit(s) Value 31:16 15:0 1536 (600h) TxNibbleCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5018h- 501Bh...

  • Page 149: Retxcnt Register

    ReTxCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5020h- 5023h Table 7-99. ReTxCnt Register Reset Bit(s) Value 31:4 Reserved: Always read as 0. ReTxCnt: This counter keeps track of the number of times a retransmission has occurred. The final count is loaded in statistics vectors.

  • Page 150: Randomnumgen Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual MskRandomNum Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5028h - 502Bh Reset Bit(s) Value 31:10 TotalTxCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5034h- 5037h Reset Bit(s) Value...

  • Page 151: Rxbytecnt Register

    RxByteCnt Register Type: R/W Internal Registers Subgroup: MAC Registers Byte Address: 5040h- 5043h Table 7-103. RxByteCnt Register Reset Bit(s) Value 31:16 Reserved: Always reads 0. 15:0 RxByteCnt: This is a multipurpose counter used internally to count the number of bytes at different times. It should only be written for test purposes, such as testing huge frame functionality.

  • Page 152: Miistatus Register

    Reserved: Always read as 0. MIILink Fail: MII Link Fail indicator. Setting this bit indicates to the current PHY that the AIC-6915 is continuously scanning for link status. The external PHY’s Status register’s (Register 1) bit 2, has failed. This bit is cleared during normal operation.
  • Page 153 Since each external PHY takes up 128 bytes (32 x 32 bits), the actual address offset to access each of them through the AIC-6915 is: Table 7-107. External PHY Address Examples External PHY PHY # 0 PHY # 1 PHY # 2...

  • Page 154: Address Filtering Registers

    Table 7-108 starts at byte address 6000h from the internal registers base address, offset 56000h from the AIC-6915’s base address. No bits have reset values, so all bits corresponding to enabled functions must be written. Note that word 3 is not used, and that data is transferred only on the lower 16-bits of words 2, 1, and 0.
  • Page 155 VLAN table. If the VLAN number matches, the frame is accepted. When in VLAN mode, the adapter can belong to up to 32 VLANs. The AIC-6915 compares the VLAN number against all of the entries in the table. So, for example, if the adapter is a member of only one VLAN, all of the entries should be the same.

  • Page 156: Mac Statistic Registers

    AIC-6915 Ethernet LAN Controller Programmer’s Manual MAC Statistic Registers Type: R/W Internal Registers Subgroup: MAC Statistic Byte Address: 7000h - 7FFFh The following are a list of statistics counters tracked by the MAC block. The “Source” field indicates the internal logic block that generates the statistics. The “Priority” field indicates 802.3 priority;...
  • Page 157 Table 7-109. MAC Statistic Register (Continued) Byte Addr Statistics Source Frames Lost due to Internal Transmit Errors. (Cannot recover from FIFO underrun) Receive OK Frames (RX) Receive CRC Errors (RX) Alignment Errors (RX) Receive OK Octets. (RX) Pause Frames Received OK. (RX) Control Frames Received OK.
  • Page 158 AIC-6915 Ethernet LAN Controller Programmer’s Manual Table 7-109. MAC Statistic Register (Continued) Byte Addr Statistics Receive Packets 128 to 255 Bytes Receive Packets 256 to 511 Bytes Receive Packets 512 to 1023 Bytes Receive Packets 1024 to 1518 Bytes Frames Lost Due to Internal Receive Errors.

  • Page 159: Transmit Frame Processor Register

    Transmit Frame Processor - TxGfpMem Type: R/W Internal Registers Subgroup: Transmit Frame Processor Register Byte Address: 8000h-9FFFh Table 7-110. Transmit Frame Processor Register Reset Bit(s) Value 31:0 TxGfpMem: This field defines a 256-byte address space that the software driver can use to access the transmit General Frame Processor program memory.

  • Page 161: Sample Driver

    The following sample driver documentation is intended as a guide for the software developer writing a device driver for the Adaptec AIC-6915 Ethernet Network Controller. It is designed to complement the driver source code in the DDK and to serve as a basic checklist for driver development.

  • Page 162: Producer-Consumer Model For The Aic-6915

    The AIC-6915 uses the Producer-Consumer model for its operation and interaction with the driver. One of the entities (AIC-6915 or the driver) "Produces" work items by placing them in a shared queue, the other entity "Consumes" the work items by dequeueing them from the queue.

  • Page 163: Basic Register Initialization And Reset Sequence

    The first step in the initialization process is NIC recognition. The most straightforward method of finding the card is through PCI configuration space. Operating system-specific calls may be used to locate the device with the AIC-6915 Device ID (6915) and Vendor ID (9004).

  • Page 164: Pci Command Register

    AIC-6915 Ethernet LAN Controller Programmer’s Manual PCI C Register (offset 04h): The PCI Command register must be initialized OMMAND to enable memory and/or I/O register access, to enable bus master mode, to enable Memory Write and Invalidate, and to enable system error response. The Command register does not have to be reinitialized for a reset operation.
  • Page 165 InterruptStatus (offset 80h): The InterruptStatus register should be set to zero during initialization. There are two types of status bits - those that are cleared on read or write, and others that must be cleared at the source. InterruptEnable (offset 88h): This register indicates which events should trigger an interrupt.
  • Page 166 // Receive Initialization (see example below) // Transmit Initialization (see example below) // After all other pertinent AIC-6915 registers have been initialized, the // controller must be enabled. // be enabled, as well as the Receive and Transmit engines. These bits are all // contained in the GeneralEthernetCtrl register.

  • Page 167: Receive Process

    // The hardware is now ready to transmit and receive packets! Receive Process The receive process in the AIC-6915 is based on the use of a receive completion queue and receive buffers. Their relationship is discussed below. Receive Completion Descriptor Queue When a packet has been received and DMA-transferred to host memory, the AIC-6915 adds a new entry to the Receive Completion Descriptor Queue.

  • Page 168: Receive Buffer Descriptor Queue

    The third word contains a partial TCP/UDP checksum and a VLAN ID and priority. The fourth word is a packet timestamp. To program the AIC-6915 to use a Type 3 descriptor, the developer must set R...

  • Page 169: Two Receive Queues

    VLAN priority, or on priority as defined in the Perfect Addressing table. Receive Producer/Consumer Model There are two different receive models available in the AIC-6915. One option is to use a producer-consumer model to manage receive resources. In this case, the software is the producer of Receive Buffer Descriptors, since it makes the receive buffer resource available at initialization time and also again after processing each receive interrupt.
  • Page 170 AIC-6915 Ethernet LAN Controller Programmer’s Manual OMPLETION UEUE location and type of the first Receive Completion Descriptor Queue. Required Fields: – RxCompletionQ1BaseAddress: Assign the base address of Receive Completion Descriptor Queue 1 in hardware. – RxCompletionQ1Type: Select the type of the Receive Completion Descriptor.
  • Page 171 (offset D0h): This register controls receive DMA operation and frame acceptance criteria. Required Fields: – RxCompletionQ2Enable: Enable the second Receive Completion Descriptor Queue if needed. – RxDmaQueueMode: Select the queue sorting criteria, if a second queue is needed. Sorting may be based on packet size or priority. (offset D4h): This register defines Receive Buffer Descriptor UEUE Queue 1.
  • Page 172 AIC-6915 Ethernet LAN Controller Programmer’s Manual UEUE indices for the first Receive Buffer Descriptor Queue. Initialization of this register depends on the choice of the receive model - producer-consumer versus polling. Required Fields: – RxDescQ1Consumer = 0: Initialize the consumer index to zero.
  • Page 173 Sample Driver // assign the base address of the completion queue (high 24 bits) RxCompletionQueue1CtrlValue.RxCompletionQ1BaseAddress = NdisGetPhysicalAddressLow(RxCompletionQ) >> 8; // Write the value to the AIC-6915 AIC6915_WRITE_REG(Adapter->RegisterBaseVa->RxCompletionQueue1Ctrl, RxCompletionQueue1CtrlValue); // Single completion queue - use default value for RxCompletionQueue2Ctrl // Initialize Tx and Rx Completion Queue consumer and producer indices to zero AIC6915_WRITE_REG(Adapter->RegisterBaseVa->CompletionQueue1ConsumerIndex,...
  • Page 174 AIC-6915 Ethernet LAN Controller Programmer’s Manual // If single queue, use the first queue only // Initialize RxDescQueue1LowAddress // Allocate memory for RxDescQueue1 AIC6915_ALLOC_MEMORY(&Status, &RxDescQ, 4 * 2048); // 4 byte descriptor, //2K fixed size queue RxDescQueue1LowAddressvalue.Reserved = 0; // assign the buffer address RxDescQueue1LowAddrValue.RxDescQ1LowAddress =...

  • Page 175: Receive Interrupt Handling

    Receive Interrupt Handling When a packet is received, the AIC-6915 adds a new entry to the Receive Completion Descriptor Queue and generates either an E (or R enabled. When the driver processes this interrupt, it must first read the Receive Completion Queue consumer and producer indices.

  • Page 176: Transmit Process

    Adapter->RxDescQProducerIndex = RxDescIndex; // We’re done with receives! Transmit Process The transmit process in the AIC-6915 utilizes the producer-consumer model. It is based on a transmit completion queue and transmit buffers. The relationship between Completion and Buffer Descriptors is discussed below.

  • Page 177: Transmit Completion Descriptor Types

    Transmit Producer Index of zero. The Transmit Buffer Descriptor contains the data to be transmitted by the AIC-6915. Since the driver is the producer of Transmit Buffer Descriptors, it is responsible for defining the fragment counts and addresses in the buffer.

  • Page 178: Transmit Buffer Descriptor Types

    AIC-6915 Ethernet LAN Controller Programmer’s Manual of descriptor. These descriptors are outlined below. For a complete description, refer to the Transmit Architecture section. All hardware indices which reference a Transmit Buffer Descriptor are incremented by a value which is dependent upon the size of the descriptor. The size of the descriptor will vary, depending upon the descriptor type, skip field option, and number of buffers in the descriptor for Type 0 and Type 4 descriptors.
  • Page 179 Transmit Producer or Consumer index to a software array index. The size of a Type 1 descriptor in bytes is calculated using the formula: (8 + S IELD For example, assume that a Type 1 descriptor is in use, with a 16-byte skip field. The size of the descriptor is then 24 bytes.

  • Page 180: Two Transmit Queues

    Priority bit in the Completion Descriptor. Transmit Producer-Consumer Model The AIC-6915 uses a producer-consumer model to manage transmit resources. The driver is the producer of transmit packets, so the Transmit Buffer Descriptor producer index must be maintained by software.

  • Page 181: Transmit Initialization

    Transmit Initialization The AIC-6915 provides a set of registers which must be initialized in preparation for transmitting packets. These registers and the fields which must be initialized in the driver are summarized below. Register bits which are not explicitly described here may be left at the default reset value.
  • Page 182 Transmit Buffer Descriptor Queues. These fields are incremented whenever the AIC-6915 transmits a packet. The consumer index, just as the producer index, is more appropriately referred to as an offset. It is an offset to the next packet in the Transmit Buffer Descriptor Queue, in units of 8 bytes, and therefore is dependent upon the type of descriptor.
  • Page 183 Required Fields: – RxCompletionQ1ConsumerIndex = 0: Initialize the Receive Completion Descriptor Queue 1 consumer index to zero. Note: this entry is also covered in the Receive Initialization section. – TxCompletionConsumerIndex = 0: Initialize the Transmit Completion Descriptor Queue consumer index to zero. OMPLETION UEUE RODUCER...
  • Page 184 AIC-6915 Ethernet LAN Controller Programmer’s Manual // Set up the low 32 bits of the low priority transmit descriptor queue // base address LoPrTxDescQBaseAddrValue = NdisGetPhysicalAddressLow(Adapter->TxDescRing.AlignedPa); AIC6915_WRITE_REG(LoPrTxDescQBaseAddr, LoPrTxDescQBaseAddrValue); // Set up the high 32 bits of address - it's 0 since we're not using // 64 bit addresses AIC6915_WRITE_REG(TxDescQHighAddr, 0);...

  • Page 185: Transmit Handling

    In the code fragment below, the operating system has called the transmit routine with a packet to be transmitted. The driver must set up the Transmit Buffer Descriptor(s) for all buffers in this packet, and then instruct the AIC-6915 controller to transmit the packet. Example:...
  • Page 186 AIC-6915 Ethernet LAN Controller Programmer’s Manual // Put each physical segment for this buffer into a Transmit Buffer // Descriptor for (ii = 0 ; ii < BufferPhysicalSegments; ii++) PhysicalAddressUnit = PhysicalSegmentArray[ii] ; // Get a local copy of this Transmit Buffer Descriptor TxDesc = Adapter->TxDesc[CurrentTxDescIndex];...

  • Page 187: Transmit Completion Interrupt Handling

    // Our transmit is complete! Transmit Completion Interrupt Handling After the AIC-6915 has transmitted a packet, it places that packet in the Transmit Completion Descriptor Queue and initiates a T interrupt. The driver must process this interrupt and return the transmitted packet resource to the operating system.
  • Page 188 // at that time. NdisMSendComplete( Adapter->MiniportAdapterHandle, TxComQConsumerIndex++; TxComQConsumerIndex %= AIC6915_NUMBER_OF_TX_COMPLETION_DESC; } // while (TxComQConsumerIndex != TxComQProducerIndex) // Give the Tx completion descriptors we've processed back to the AIC-6915. AIC6915_READ_REG(CompletionQ1ConsumerIndex, &CompletionQ1ConsumerReg); CompletionQ1ConsumerReg.TxCompletionConsumerIndex = TxComQConsumerIndex; AIC6915_WRITE_REG(CompletionQ1ConsumerIndex, CompletionQ1ConsumerReg); // We’re finished with all Transmit Complete processing! 8-28 sizeof(AIC6915_TX_DESC);...

  • Page 189: Aic-6915 Ddk Features

    AIC-6915 DDK Features Table 8-1 is a list of the major features available in the AIC-6915 and demonstrated in the DDK. Table 8-1. AIC-6915 DDK Features Feature Low/Hi priority Tx Buffer Option to implement one or two Descriptor Queues queues...

  • Page 190: Ddk Development Environment

    AIC-6915 Ethernet LAN Controller Programmer’s Manual DDK Development Environment The drivers contained in the DDK were written for the Windows NT environment. There is an NDIS 3.0/4.0 driver and an NDIS 5.0 driver in the DDK. They were developed using Version 5.0 of the Microsoft Visual C++ compiler.

This manual is also suitable for:

1737100

Table of Contents